Operation In Free-Run Mode - NEC V850E/Dx3 Preliminary User's Manual

16-bit Multi-Purpose Timer G (TMG)
CCSGn5
0
Free-run
mode
1
Match and
clear
mode
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Table 13-9 Interrupt output and timer output states dependent on the register
setting values
Register setting value
TBGnm SWFGnm CCSGnm
0
0
1
0
1
1
1
0
0
1
0
1
1
Note 1. An interrupt is generated only when the value of the GCCn5 register is
FFFFH.
2. An interrupt is generated only when the value of the GCCn5 register is not
FFFFH.
3. The setting of the CCSGnm bit in combination with the SWFGnm bit sets
the mode for the timing of the actualization of new compare values.
• In compare mode the new compare value will be immediately active.
• In PWM mode the new compare value will be active first after the next
overflow or match & clear of the assigned counter (TMGn0, TMGn1).

13.7 Operation in Free-Run Mode

This operation mode is the standard mode for Timer Gn operations. In this
mode the 2 counter TMGn0 and TMGn1 are counting up from 0000H to
FFFFH, generates an overflow and start again. In the match and clear mode,
which is described in Chapter 13.8 on page 462 the fixed assigned register
GCCn0 (GCCn5) is used to reduce the bit-size of the counter TMGn0
(TMGn1).
(1) Capture operation (free run)
Basic settings:
Bit
CCSGn0
CCSGn5
SWFGnm
TBGnm
Preliminary User's Manual U17566EE1V2UM00
State of each output pin
INTTMGn1 INTCCGn5
Overflow TI5 edge
interrupt detection
Overflow GCCn5
Note 1 Note 2
interrupt match
Value
0
0
0
X
Chapter 13
INTCCGnm TOGnm
TIm edge
detection
Tied to inactive
GCCnm match
level
TIm edge
detection
PWM
CMPGm match
(free run)
TIm edge
detection
Tied to inactive
GCCnm match
level
TIm edge
detection
PWM
CMPGm match
(match and clear)
Remark
free run mode
disable TOGnm
assign counter
for GCCnm
0: TMGn0
1: TMGn1
451