NEC V850E/Dx3 Preliminary User's Manual page 405

16-bit Timer/Event Counter P (TMP)
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When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the
valid edge input to the TIPnm pin is detected, the count value of the 16-bit
counter is stored in the TPnCCRm register, and a capture interrupt request
signal (INTTPnCCm) is generated.
The 16-bit counter continues counting in synchronization with the count clock.
When it counts up to FFFFH, it generates an overflow interrupt request signal
(INTTPnOV) at the next clock, is cleared to 0000H, and continues counting. At
this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Clear the
overflow flag to 0 by executing the CLR instruction by software.
FFFFH
16-bit counter
0000H
TPnCE bit
TIPn0 pin input
TPnCCR0 register
INTTPnCC0 signal
TIPn1 pin input
TPnCCR1 register
INTTPnCC1 signal
INTTPnOV signal
TPnOVF bit
Figure 11-27 Basic timing in free-running timer mode (capture function)
Preliminary User's Manual U17566EE1V2UM00
D
10
D
11
D
00
D
01
D
02
D D
00 01
D D
10 11
Cleared to 0 by Cleared to 0 by
CLR instruction CLR instruction
Chapter 11
D
12
D
13
D
03
D D
02 03
D D
12 13
Cleared to 0 by
CLR instruction
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