Description - NEC V850E/Dx3 Preliminary User's Manual

Chapter 23
SPCLK0 (16 MHz)
SPCLK1 (8 MHz)
SPCLK2 (4 MHz)
SPCLK5 (500 KHz)
824
Downloaded from Elcodis.com electronic components distributor
Note 1. The programmer has to make sure that the timing requirements of the
external LCD controller are met.
2. For electrical characteristics please refer to the Electrical Target
Specification.
3. If the concerned pins are configured as LCD Bus Interface pins change
between input and output is performed automatically by LCD Bus Interface
read and write operations. Refer also to "Port group 9" on page 85.

23.1.1 Description

Data can be read from and written to the LCD Bus Interface by either involving
the DMA Controller or by directly accessing the interface from the CPU. The
timing of the external bus signals is determined by register settings (WST and
CYC).
The LCD Bus Interface is 8 bits wide. In order to improve performance, the
interface is equipped with a 32-bit register that allows the CPU or DMA to
access the data register with 8-, 16-, or 32-bit data accesses. The interface
automatically generates 1, 2, or 4 consecutive (8-bit) accesses on the external
bus.
The LCD Bus Interface has an internal 32-bit write buffer that allows the next
data to be written to the data register (LBDATA0) while a transfer on the
external bus interface is in progress.
The following figure shows the main components of the LCD Bus Interface.
LBCTL0
Register set
Clock
selector
Timing
generator
Figure 23-1 LCD Bus Interface block diagram
As shown in the figure, the result of a read operation is directly available in the
LBDATA0 and LBDATAR0 registers. For data output, the contents of the
LBDATA0 register is copied to the 32-bit write buffer.
Preliminary User's Manual U17566EE1V2UM00
Internal bus
LBDATA0
LBCYC0 LBWST0
LBDATAR0
Control
mod80/
mod68
selector
LCD Bus Interface (LCD-I/F)
Write
buffer
DBD[7:0]
DBWR (R/W)
DBRD (E)
INTLCD