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16-bit Multi-Purpose Timer G (TMG)
Bit position
15, 11, 7, 3
14, 10, 6, 2
13, 9, 5, 1
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OCTLGn - Timer Gn output control register
This register controls the timer output from the TOGnm pin and the capture or
compare modus for the GCCnm register.
Access
This register can be read/written in 16-bit, 8-bit or 1-bit units.
The low byte OCTLGn.bit[7:0] is accessible separately under the name
OCTLGnL, the high byte OCTLGn.bit[15:8] under the name OCTLGnH.
Address
OCTLGn, OCTLGnL:
OCTLGnH:
Initial Value
4444
. This register is cleared by any reset.
H
15
SWFGn4
ALVGn4
R/W
R/W
7
SWFGn2
ALVGn2
R/W
R/W
Caution
1.
When the POWERn bit is set, the rewriting of CCSGnm is prohibited
2.
When the POWERn bit and TMGn0E bit (TMGn1E bit) are set at the same
time, the rewriting of the ALVGnm bits is prohibited.
Table 13-6
OCTLGn register contents
Bit name
Function
SWFGnm
Fixes the TOGnm pin output level according to the setting of ALVGnm bit.
0: disable TOGnm to inactive level
1: enable TOGnm
ALVGnm
Specifies the active level of the TGOnm pin output.
0: Active level is 0
1: Active level is 1
Caution:
CCSGnm
Specifies Capture/Compare mode selection:
0: Capture mode:
if external edge is detected the INTCCGnm interrupt occurs, the
corresponding counter value is written to GCCnm
1: Compare mode:
if GCCnm matches with corresponding timebase the INTCCGnm interrupt
occurs, if SWFGm is set the PWM output mode is set
Caution:
Preliminary User's Manual U17566EE1V2UM00
<base> + 4
H
<base> + 5
H
14
13
12
CCSGn4
0
SWFGn3
R/W
R/W
6
5
4
CCSGn2
0
SWFGn1
R/W
R/W
Don't write this bit, before ENFGn0 or ENFGn1 of TMGSTn is 0, so first
clear TMGn0E or TMGn1E bit of the TMGMn register and check
ENFGn0 or ENFGn1 bit before writing.
Don't write this bit, before POWERn bit of TMGMnH is 0.
Chapter 13
11
10
9
ALVGn3
CCSGn3
R/W
R/W
R/W
3
2
1
ALVGn1
CCSGn1
R/W
R/W
R/W
8
0
R/W
0
0
R/W
445
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