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Chapter 16
Bit position
7
6
5
4 to 2
1
0
a)
Before starting the SBF transmission by UAnOPT0.UAnSTT = 1 make sure that no data transfer is ongoing,
that means check that UAnSTR.UAnTSF = 0.
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Table 16-4
UAnOPT0 register contents
Bit name
Function
UAnSRF
SBF reception flag:
0: When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnRXE bit = 0 are set.
Also upon normal end of SBF reception.
1: During SBF reception
• SBF (Sync Brake Field) reception is judged during LIN communication.
• The UAnSRF bit is held at 1 when an SBF reception error occurs, and then
SBF reception is started again.
UAnSRT
SBF reception trigger:
0: –
1: SBF reception trigger
• This is the SBF reception trigger bit during LIN communication, and when
read, "0" is always read. For SBF reception, set the UAnSRT bit (to 1) to
enable SBF reception.
• Set the UAnSRT bit after setting the UAnPWR bit = UAnRXE bit = 1.
UAnSTT
SBF transmission trigger:
0: –
1: SBF transmission trigger
• This is the SBF transmission trigger bit during LIN communication, and when
read, "0" is always read.
• Set the UAnSTT bit after setting the UAnPWR bit = UAnTXE bit = 1.
UAnSBL[2:0]
SBF transmission length selection:
UAnSBL2
1
1
1
0
0
0
0
1
This register can be set when the UAnPWR bit = 0 or when the UAnTXE bit = 0.
UAnTDL
Transmit data level bit
0: Normal output of transfer data
1: Inverted output of transfer data
• The output level of the TXDAn pin can be inverted using the UAnTDL bit.
• This register can be set when the UAnPWR bit = 0 or when the UAnTXE bit =
0.
UAnRDL
Receive data level bit
0: Normal input of transfer data
1: Inverted input of transfer data
• The output level of the RXDAn pin can be inverted using the UAnRDL bit.
• This register can be set when the UAnPWR bit = 0 or the UAnRXE bit = 0.
Preliminary User's Manual U17566EE1V2UM00
Asynchronous Serial Interface (UARTA)
a
UAnSBL1
UAnSBL0 SBF transmission length
0
1
13-bit output (default value)
1
0
14-bit output
1
1
15-bit output
0
0
16-bit output
0
1
17-bit output
1
0
18-bit output
1
1
19-bit output
0
0
20-bit output
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