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I
C Bus (IIC)
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Processing by master device
←
IICn
IICn
address
ACKDn
STDn
SPDn
WTIMn
H
ACKEn
H
MSTSn
STTn
L
SPTn
WRELn
INTIICn
TRCn
Transfer lines
1
2
3
SCL0n
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDA0n
Start condition
Processing by slave device
IICn
ACKDn
STDn
SPDn
WTIMn
H
ACKEn
H
L
MSTSn
STTn
L
L
SPTn
WRELn
L
INTIICn
TRCn
Figure 18-22
Example of slave to master communication
(when 9-clock wait is selected for both master and slave) (1/3)
(a) start condition ~ address
Note
To cancel master wait, write FFH to IICn or set WRELn.
Preliminary User's Manual U17566EE1V2UM00
4
5
6
7
8
9
R
Chapter 18
←
IICn
FFH Note
Note
1
2
3
4
5
6
D7
D6
D5
D4
D3
D2
←
IICn
data
635
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