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DMA Controller (DMAC)
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8.7 DMA Channel Priorities
The DMA channel priorities are fixed as follows.
DMA channel 0 > DMA channel 1 > ... > DMA channel n
In the single-step transfer mode, the DMA Controller releases the buses after
each byte/half-word/word transfer. If a higher priority DMA transfer request is
issued while the bus is released, the higher priority DMA transfer request is
acknowledged.
In the block transfer mode, the channel used for transfer is never switched.
8.8 DMA Transfer Start Factors
There are two types of DMA transfer start factors, as shown below.
(1)
Request from on-chip peripheral I/O
If the ENn and the TCn bits of the DCHCn register are set as shown below, and
an interrupt request is issued from the on-chip peripheral I/O that is set in the
DTFRn register, the DMA transfer starts.
• ENn bit = 1
• TCn bit = 0
(2)
Request from software
If the STGn, the ENn and the TCn bits of the DCHCn register are set as
follows, the DMA transfer starts.
• STGn bit = 1
• ENn bit = 1
• TCn bit = 0
8.9 Forcible Interruption
DMA transfer can be forcibly interrupted by NMI input during DMA transfer. At
such a time, the DMAC clears the ENn bit of the DCHCn register of all
channels and the DMA transfer disabled state is entered. An NMI request can
then be acknowledged after the DMA transfer executed during NMI input is
terminated.
In block transfer mode, the DMA transfer request is held in the DMAC. If the
ENn bit is set back to "1", the DMA transfer is resumed from the point where it
was interrupted.
In the single transfer mode, if the ENn bit is set back to "1", the next DMA
transfer request is acknowledged and DMA transfer is resumed.
Preliminary User's Manual U17566EE1V2UM00
Chapter 8
325
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