NEC V850E/Dx3 Preliminary User's Manual page 111

CPU System Functions
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(4) EIPSW, FEPSW, DBPSW, CTPSWPSW saving registers
The PSW saving registers save the contents of the program status word for
different occasions, see Table 3-4.
When one of the occasions listed in Table 3-4 occurs, the current value of the
PSW is saved to the saving registers.
All PSW saving registers are built up as the PSW, with the initial value
0000 0xxx (x = undefined).
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Table 3-7 PSW saving registers
Register
Status saving register
during interrupt
Status saving register
during non-maskable
interrupts
Status saving register
during exception/debug
trap
Status saving register
during CALLT execution
a)
Reading from this register is only enabled between a DBTRAP exception (excep-
tion handler address 0000 0060
instruction. DBTRAP exceptions are generated upon ILGOP and ROM Correction
detections (refer to "Interrupt Controller (INTC)" on page 187 and "ROM Correction
Function (ROMC)" on page 331).
Note When multiple interrupt servicing is enabled, the contents of EIPSW or
FEPSW must be saved by program—because only one PSW saving register
for maskable interrupts and non-maskable interrupts is provided, respectively.
Caution Bits 31 to 26 of EIPC and bits 31 to 12 and 10 to 8 of EIPSW are reserved for
future function expansion (fixed to 0).When setting the value of EIPC, FEPC, or
CTPC, use even values (bit 0 = 0).
If bit 0 is set to 1, the setting of this bit is ignored. This is because bit 0 of the
program counter is fixed to 0.
Preliminary User's Manual U17566EE1V2UM00
Shortcut Saves contents of PSW in case of
EIPSW • software exception
• maskable interrupt
FEPSW • non-maskable interrupt
a
DBPSW • exception trap
• debug trap
• debug break
• during a single-step operation
CTPSW • execution of CALLT instruction
) and the exception handler terminating DBRET
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Chapter 3
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