NEC V850E/Dx3 Preliminary User's Manual page 417

16-bit Timer/Event Counter P (TMP)
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(d) Processing of overflow if capture trigger interval is long
If the pulse width is greater than one cycle of the 16-bit counter, care must
be exercised because an overflow may occur more than once from the first
capture trigger to the next. First, an example of incorrect processing is
shown below.
FFFFH
16-bit counter
0000H
TPnCE bit
TIPnm pin input
TPnCCRm register
INTTPnOV signal
TPnOVF bit
Figure 11-35 Example of incorrect processing when capture trigger interval is long
The following problem may occur when long pulse width is measured in the
free-running timer mode.
<1> Read the TPnCCRm register (setting of the default value of the
TIPnm pin input).
<2> An overflow occurs. Nothing is done by software.
<3> An overflow occurs a second time. Nothing is done by software.
<4> Read the TPnCCRm register.
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by
(10000H + D
Actually, the pulse width must be (20000H + D
overflow occurs twice.
Preliminary User's Manual U17566EE1V2UM00
D
m0
D
m0
1 cycle of 16-bit counter
Pulse width
<1> <2>
- D
) (incorrect).
m1 m0
Chapter 11
D
m1
D
m1
<3> <4>
- D
) because an
m1 m0
417