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Clock Generator
Bit position
1 to 0
Write protection
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Table 4-7
PCC register contents (2/2)
Bit name
Function
CKS[1:0]
Processor clock connection:
CKS1
0
0
1
1
As long as PCC.CLS = 1 these bits are ignored. For changing the processor clock
source these bits must be written. By this CLS is set to 0 automatically.
Note
1.
Switching to an unstable or not available clock is not protected by
hardware. You must monitor the CGSTAT register or count the required
stabilization time by software before switching to make sure not to select
an unstable clock source.
Ensure also that the stabilization times of the PLL and SSCG (refer to the
Electrical Target Specification) have elapsed before using any PLL or
SSCG output clock.
2.
Switching to sub clock after Sub-WATCH and WATCH mode release is
monitored in the CLS flag. The CLS flag can not be changed to 1 by
software.
3.
FRC, MFRC and SOSCP are not changed when power save modes are
entered or released.
Write protection of this register is achieved in two ways:
• The register can be written only once after any reset.
• The register is protected by a special sequence via the PHCMD register.
A fail of a write by the special sequence is reflected by PHS.PRERR = 1.
If a write is correctly performed by the special sequence after the register has
already once been written successfully PHS.PRERR remains 0, though the
write has been ignored.
PHS.PRERR shows violations of the special sequence only. It does not reflect
attempts to write the register more than once after reset or power save mode
wake-up.
Preliminary User's Manual U17566EE1V2UM00
CKS0
Selected clock connection
Main oscillator
0
SSCG
1
PLL (main oscillator frequency x4)
0
PLL (main oscillator frequency x8)
1
Chapter 4
143
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