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Chapter 19
DBT length
25
24
24
23
23
23
22
22
22
22
21
21
21
21
21
20
20
20
20
20
20
19
19
19
19
19
19
19
18
18
18
18
18
18
18
18
17
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Table 19-27 shows the combinations of bit rates that satisfy the above
conditions.
Table 19-27
Settable bit rate combinations (1/3)
Valid bit rate setting
SYNC
PROP
SEGMENT
SEGMENT
1
8
1
7
1
9
1
6
1
8
1
10
1
5
1
7
1
9
1
11
1
4
1
6
1
8
1
10
1
12
1
3
1
5
1
7
1
9
1
11
1
13
1
2
1
4
1
6
1
8
1
10
1
12
1
14
1
1
1
3
1
5
1
7
1
9
1
11
1
13
1
15
1
2
Preliminary User's Manual U17566EE1V2UM00
CnBTR register setting
PHASE
PHASE
TSEG13 to
SEGMENT1
SEGMENT2
8
8
8
8
7
7
8
8
7
7
6
6
8
8
7
7
6
6
5
5
8
8
7
7
6
6
5
5
4
4
8
8
7
7
6
6
5
5
4
4
3
3
8
8
7
7
6
6
5
5
4
4
3
3
2
2
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
7
7
CAN Controller (CAN)
Sampling
value
point
TSEG22 to
(unit %)
TSEG10
TSEG20
1111
111
68.0
1110
111
66.7
1111
110
70.8
1101
111
65.2
1110
110
69.6
1111
101
73.9
1100
111
63.6
1101
110
68.2
1110
101
72.7
1111
100
77.3
1011
111
61.9
1100
110
66.7
1101
101
71.4
1110
100
76.2
1111
011
81.0
1010
111
60.0
1011
110
65.0
1100
101
70.0
1101
100
75.0
1110
011
80.0
1111
010
85.0
1001
111
57.9
1010
110
63.2
1011
101
68.4
1100
100
73.7
1101
011
78.9
1110
010
84.2
1111
001
89.5
1000
111
55.6
1001
110
61.1
1010
101
66.7
1011
100
72.2
1100
011
77.8
1101
010
83.3
1110
001
88.9
1111
000
94.4
1000
110
58.8
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