Description - NEC V850E/Dx3 Preliminary User's Manual

Chapter 24
SG0CLK =
PCLK0
(16MHz)
Tone generator
842
Downloaded from Elcodis.com electronic components distributor

24.1.1 Description

The following figure provides a functional block diagram of the Sound
Generator.
Clear
1
9-bit S0GFL
frequency counter
0
SG0CTL.PWR
SG0FL
SG0FL
frequency low register frequency compare buffer
CPU write to
SG0PWM
Match
SG0PWM
volume compare buffer
SG0PWM
volume register
Figure 24-1 Sound Generator block diagram
The Sound Generator's input clock SG0CLK is the 16 MHz clock PCLK0.
The tone generator consists of two up-counters with compare registers. The
values written to the frequency registers are automatically copied to compare
buffers. The counters are reset to zero when their values match the contents of
the associated compare buffers.
The 9-bit counter SG0FL generates a clock with a frequency between 32 KHz
and 64 KHz. This clock constitutes the PWM frequency.
It is also the input of the second 6-bit counter SG0FH. The resulting tone signal
behind the by-two-divider has a frequency between 245 Hz and 6 KHz and a
50 % duty cycle.
PWM The PWM modulates the duty cycle according to the desired volume. It is
controlled by the volume register SG0PWM. The value written to this register is
automatically copied to the associated volume compare buffer.
The PWM continually compares the value of the counter SG0FL with the
contents of its volume compare buffer.
The RS flipflop of the PWM is set by the pulses generated by the counter
SG0FL. It is reset when the SG0FL counter value matches the contents of the
volume buffer. Thus, the PWM output signal can have a duty cycle between
0 % (null volume) and 100 % (maximum volume).
The PWM frequency is above 32 KHz and hence outside the audible range.
Outputs The Sound Generator is connected to the pins SGO and SGOA. By default, pin
SGO provides the tone signal SG0OF and pin SGOA the PWM signal SG0OA
that holds the volume ("amplitude") information.
If bit SG0CTL.OS is set, pin SGO provides the composite signal SG0O that
can directly control a speaker circuit.
Preliminary User's Manual U17566EE1V2UM00
Clear
6-bit S0GFH 9-bit S0GFH
tone counter
f Tone
PWM
(32 to 64 kHz)
Match
Match
&
SG0FH
tone compare buffer
Load
Load
SG0FH
frequency high register
f
PWM
(32 to 64 kHz)
&
Load
Y
= 0?
Sound Generator (SG)
/2
f
Tone
(245 Hz to
6 kHz)
2 x f
Tone
(490 Hz to
12 kHz)
SG0CTL.OS
Tone
SG0OF
0
SGO
SG0
&
1
S
RS-FF SG0OA
SG0A
f
Reset
R
PWM
(min. 32 kHz)
PWM