Block Transfer Mode - NEC V850E/Dx3 Preliminary User's Manual

Chapter 8
DMA Transfer
Request CH0
DMA Transfer
Request CH2
DMA Transfer
Request CH3
DMA Transfer
Request CH2
DMA Transfer
Request CH3
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Figure 8-8 shows a single transfer mode example in which two or more lower
priority DMA transfer requests are generated within one clock after the end of a
single transfer. DMA channels 0, 2 and 3 are used for this single transfer
example. When three or more DMA transfer request signals are activated at
the same time always the two highest priority DMA transfers are performed
alternately.
Note Note Note
CPU DMA3 CPU DMA3 CPU DMA2 CPU
Figure 8-8 Single transfer example 4
Note The bus is always released

8.12.2 Block transfer mode

In the block transfer mode, once transfer begins, the DMAC continues the
transfer operation without releasing the bus until a terminal count occurs. No
other DMA requests are acknowledged during block transfer.
After the block transfer ends and the DMAC releases the bus and another DMA
transfer can be acknowledged.
Figure 8-9 shows a block transfer mode example. It is a block transfer mode
example in which a higher priority DMA transfer request is generated. DMA
channels 2 and 3 are used for the block transfer example.
CPU CPU CPU DMA3 DMA3
Figure 8-9 Block transfer example
Preliminary User's Manual U17566EE1V2UM00
Note Note Note
DMA0 CPU DMA2 CPU DMA0 CPU DMA2 CPU
DMA channel 0
terminal count
DMA3 DMA3 DMA3 DMA3 DMA3 DMA3
DMA channel 3
terminal count
DMA Controller (DMAC)
Note Note Note
DMA3 CPU DMA2 CPU DMA3 CPU CPU
DMA channel 3
terminal count
DMA channel 2
terminal count
CPU DMA2 DMA2 DMA2 DMA2 DMA2
The bus is always released