NEC V850E/Dx3 Preliminary User's Manual page 406

Chapter 11
TPnCTL0
TPnCTL1
TPnIOC0
406
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(1) Register setting in free-running timer mode
(a) TMPn control register 0 (TPnCTL0)
TPnCE
0/1 0 0
Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1
(b) TMPn control register 1 (TPnCTL1)
TPnEST TPnEEE
0 0 0/1 0
(c) TMPn I/O control register 0 (TPnIOC0)
0 0 0 0
Preliminary User's Manual U17566EE1V2UM00
16-bit Timer/Event Counter P (TMP)
TPnCKS2 TPnCKS1 TPnCKS0
0 0 0/1 0/1
TPnMD2 TPnMD1 TPnMD0
0 1 0
TPnOL1 TPnOE1 TPnOL0 TPnOE0
0/1 0/1 0/1
0/1
Note
Select count clock
0: Stop counting
1: Enable counting
1
1, 0, 1:
Free-running mode
0: Operate with count
clock selected by
TPnCKS0 to TPnCKS2 bits
1: Count on external
event count input signal
0/1
0: Disable TOPn0 pin output
1: Enable TOPn0 pin output
Setting of output level with
operation of TOPn0 pin disabled
0: Low level
1: High level
0: Disable TOPn1 pin output
1: Enable TOPn1 pin output
Setting of output level with
operation of TOPn1 pin disabled
0: Low level
1: High level