NEC V850E/Dx3 Preliminary User's Manual page 153

Clock Generator
Bit position
2, 0
Write protection
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Table 4-14 TCC register contents (2/2)
Bit name Function
WTSOS, Clock source for Watch Timer and LCD controller:
WTSEL0
WTSOS
0
1
0
1
By default, the sub oscillator is disabled in STOP mode (see bit WCC.SOSTP). If
WCC.SOSTP is 1, choose main or ring oscillator before entering STOP mode.
Caution: Do not specify the sub oscillator, if the sub oscillator is not enabled or
not connected.
Note Only POC and external RESET can clear the TCC register. Only one write
access to TCC is allowed after reset release. Once the TCC has been written,
it ignores new write accesses until the next POC or external RESET is issued.
Write protection of this register is achieved in two ways:
• The register can be written only once after Power-On-Clear reset or external
RESET.
• The register is protected by a special sequence via the PHCMD register.
A fail of a write by the special sequence is reflected by PHS.PRERR = 1.
If a write is correctly performed by the special sequence after the register has
already once been written successfully PHS.PRERR remains 0, though the
write has been ignored.
PHS.PRERR shows violations of the special sequence only. It does not reflect
attempts to write the register more than once after reset.
Preliminary User's Manual U17566EE1V2UM00
WTSEL0 Clock source
Ring oscillator
0
Sub oscillator
0
Main oscillator
1
Setting prohibited
1
Chapter 4
153