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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
5.3.5 In-service priority register (ISPR)
This register holds the priority level of the maskable interrupt currently accepted. When an interrupt request is
accepted, the bit of this register corresponding to the priority level of that interrupt is set to 1 and remains set while
the interrupt is serviced.
When the RETI instruction is executed, the bit corresponding to the interrupt request having the highest priority
is automatically reset to 0 by hardware. However, it is not reset when execution is returned from non-maskable
processing or exception processing.
This register can be only read in 8- or 1-bit units.
7
6
ISPR
ISPR7
ISPR6
Bit Position
Bit Name
7 to 0
ISPR7 to
ISPR0
Remark
n: 0 to 7 (priority level)
5.3.6 Maskable interrupt status flag (ID)
The interrupt disable status flag (ID) of the PSW controls the enabling and disabling of maskable interrupt requests.
31
PSW
0
0
0
0
0
Bit Position
Bit Name
5
ID
118
5
4
3
ISPR5
ISPR4
ISPR3
In-Service Priority Flag
Indicates priority of interrupt currently accepted
0: Interrupt request with priority n not accepted
1: Interrupt request with priority n accepted
0
0
0
0
0
0
0
0
0
0
0
Interrupt Disable
Indicates enabling/disabling of maskable interrupt processing.
0: Maskable interrupt accepting enabled
1: Maskable interrupt accepting disabled (pending)
It is set to 1 by the DI instruction and reset to 0 by the EI instruction. Its value is
also modified by the RETI instruction or LDSR instruction when referencing the
PSW.
Non-maskable interrupt and exceptions are acknowledged regardless of this flag.
When a maskable interrupt is accepted, ID flag is automatically set to 1 by
hardware.
The interrupt request generated during the accepting disabled period (ID:1) is
accepted when the xxIFn bit of xxICn is set to 1, and ID flag is reset to 0.
User's Manual U11969EJ3V0UM00
2
1
0
ISPR2
ISPR1
ISPR0
Function
8
7
6
5
0
0
0
0
0
0
0
0
NP
EP
ID
SAT
Function
Address
After reset
FFFFF166H
00H
4
3
2
1
0
After reset
CY
OV
S Z
00000020H
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