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Chapter 5
INTM0
R/W
Reset
INTM1
R/W
Reset
INTM2
R/W
Reset
INTM3
R/W
Reset
218
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5.4 Edge and Level Detection Configuration
The microcontroller provides the maskable external interrupts INTPn and one
non-maskable interrupt (NMI).
INTPn can be configured to generate interrupts upon edges or levels, the NMI
can be set up to react on edges.
(1)
INTM0 to INTM3 - External interrupt configuration register
External interrupt function is configured by the registers INTM0...INTM3.
7
6
5
4
0
ELSEL1
ESEL11
ESEL10
R
R/W
R/W
R/W
0
0
0
0
7
6
5
4
0
ELSEL3
ESEL31
ESEL30
R
R/W
R/W
R/W
0
0
0
0
7
6
5
4
0
ELSEL5
ESEL51
ESEL50
R
R/W
R/W
R/W
0
0
0
0
7
6
5
4
0
ELSEL7
ESEL71
ESEL70
R
R/W
R/W
R/W
0
0
0
0
The register bits ELSELn, ESELn1 and ESELn0 configure the INTPn interrupt
function:
ELSELn
ESELn1
0
0
0
0
1
1
1
1
Preliminary User's Manual U17566EE1V2UM00
3
2
1
NMIEN
ELSEL0
ESEL01
R/(W)
R/W
R/W
0
0
0
3
2
1
0
ELSEL2
ESEL21
R
R/W
R/W
0
0
0
3
2
1
0
ELSEL4
ESEL41
R
R/W
R/W
0
0
0
3
2
1
0
ELSEL6
ESEL61
R
R/W
R/W
0
0
0
ESELn0
Function
0
0
falling edge
0
1
rising edge
1
0
prohibited to use
1
1
falling and rising edge
0
0
low level detection
0
1
high level detection
1
0
low level detection
1
1
high level detection
Interrupt Controller (INTC)
0
Address
Initial value
ESEL00 FFFF F700H
00H
R/W
0
0
Address
Initial value
ESEL20 FFFF F702H
00H
R/W
0
0
Address
Initial value
ESEL40 FFFF F704H
00H
R/W
0
0
Address
Initial value
ESEL60 FFFF F706H
00H
R/W
0
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