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Chapter 7 Bus and Memory Control (BCU, MEMC)
Features summary
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Besides providing access to on-chip peripheral I/Os, the µPD70F3427
microcontroller device supports access to external memory devices (such as
external ROM and RAM) and external I/O. The Bus Control Unit BCU and
Memory Controller MEMC control the access to on-chip peripheral I/Os and to
external devices.
Since the BCU controls access to the on-chip peripherals, the registers BPC
and VSWC have to be set up correctly for all devices.
Note
Throughout this chapter, the individual chip select areas are identified by "k"
(k = 0 to 7), for example CSk for the chip select signal k or BEC.BEk0 for
setting the endian format of chip select area k.
7.1 Overview
The following external devices can be connected to the microcontroller device:
• SRAM / RAM
• ROM
• External I/O
The bus and memory control of the microcontroller device provides:
• 24 address signals (A0 to A23)
• Selectable data bus width for each chip select area
(8 bits, 16 bits and 32 bits)
• 4 chip select signals externally available (CS0, CS1, CS3 and CS4)
• Access to memory takes a minimum of two CPU clock cycles
• Up to 3 address setup wait states can be inserted for each chip select area
• Up to 7 data wait states can be inserted for each chip select area
(programmable wait)
• External data wait function through WAIT pin
• Up to 3 idle states can be inserted for each chip select area
• Up to 2 write strobe delay cycles can be inserted
• Direct Memory Access (DMA) support
• External bus mute function
Preliminary User's Manual U17566EE1V2UM00
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