NEC V850E/Dx3 Preliminary User's Manual page 468

Chapter 13
468
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Example where the data N is set, and the counter TMGn0 is selected.
0FFFH is set in GCCn0 and N < 0FFFH.
ENFG0
0FFFH
Ma tch
TM G n0
GCCn1
INTTGnCC1
INTTGnCC0
TOGn1(ALVG1=1)
TOGn1(ALVG1=0)
Figure 13-15 Timing of PWM operation (match and clear)
When 0000H is set in GCCn0 (GCCn5), the value of the counter is fixed at
0000H, and the counter does not operate. The waveform of INTCCGn0
(INTCCGn5) varies, depending on whether the count clock is the reference
clock or the sampling clock.
(a) When FFFFH is set in GCCn0 or GCCn5 (match and clear)
When FFFFH is set in GCCn0 (GCCn5), operation equivalent to the free-run
mode is performed. When an overflow occurs, INTTMGn0 (INTTMGn1) is
generated, but INTCCGn0 (INTCCGn5) is not generated.
Preliminary User's Manual U17566EE1V2UM00
16-bit Multi-Purpose Timer G (TMG)
0FFFH 0FFFH
N