Table of Contents
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Index
(ICC) 156
IIC clock select registers
(IICCLn) 588
IIC control registers
(IICCn) 579
IIC division clock select regis-
ters (OCKSn) 589
IIC flag registers (IICFn) 586
IIC function expansion registers
(IICX0n) 589
IIC shift registers (IICn) 592
IIC status registers (IICSn) 583
IICCLn 588
IICCn 579
IICFn 586
IICn 592
IICnIC 210
IICSn 583
IICX0n 589
Images in address space 115
IMRn 214
Initialization for access to exter-
nal devices 259
In-service priority register
(ISPR) 216
Instruction set 24
INT70IC 210
INT71IC 210
INTC (Interrupt Controller) 187
Internal peripheral function wait
control register (VSWC) 263
Internal RAM area 120
Internal VFB flash and ROM
area 119
Internal VSB flash area 121
Internal VSB RAM area 121
Interrupt
Maskable 203
Non-maskable 197
Processing (multiple
Response time 227
Interrupt Controller 187
Debug trap 224
Edge and level detection
Exception trap 222
Periods in which interrupts
Software exception 220
Interrupt mask registers
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Interrupt/exception source reg-
Interval measurement
INTMn 218
ISPR 216
L
LBCTL 828
LBCYC 829
LBDATA 831
LBDATA register
LBDATAR 833
LBS 272
LBWST 830
LCD
LCD Bus Interface 823
LCD Bus Interface control regis-
LCD Bus Interface cycle time
LCD Bus Interface data register
LCD Bus Interface data register
LCD Bus Interface wait state
LCD clock control register
interrupts) 225
LCD Controller/Driver 809
LCD display control register
configuration 218
LCD mode control register
are not
LCDC0 813
acknowledged 228
LCDIC 210
LCDM0 815
Preliminary User's Manual U17566EE1V2UM00
IMRn 214
ister (ECR) 112
By restarting the
counter 495
With free-running
counter 494
Access types 825
Activation of
segments 818
Panel addressing 811
Access modes 825
Interrupt generation 826
Registers 827
Timing 834
ter (LBCTL) 828
register (LBCYC) 829
(LBDATA) 831
(LBDATAR) 833
register (LBWST) 830
(LCDC0) 813
Common signals 816
Registers 812
Segment signals 817
(SEGREG0k) 815
(LCDM0) 815
Link pointer 106
Local bus size configuration
register (LBS) 272
M
Main oscillator clock monitor
register (CLMM) 163
Maskable interrupt status flag
(ID) 216
Maskable interrupts 203
Maskable Interrupts Control
Register (xxIC) 210
MCMPCnk 802
MCMPnk0 800
MCMPnk1 801
MCMPnkHW 801
MCNTCn0 799
MCNTCn1 799
MEMC (Memory
Controller) 249
Memory 119
Access configuration 282
Areas 119
Blocks 252
Controller registers 271
memory read delay configura-
tion register (RDDLY) 276
N
Noise elimination
Pin input 93
Timer G 473
Non-maskable interrupts 197
Normal operation mode 115
N-Wire
Code protection 339
Connection to
emulator 886
Controlling the
interface 882
emulator 877
Enabling methods 884
Flash programming 237
ID code 879
Security disabling 880
Security function 879
N-Wire security disable control
register (RSUDIS) 880
O
OCDM 45
OCKSn 589
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