Cpu Operation After Power Save Mode Release - NEC V850E/Dx3 Preliminary User's Manual

Clock Generator
Clock Generator re-
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5. Make sure that all DMA channels are disabled. Otherwise a DMA could
happen between steps 7 and 8, and the power down mode may not be
entered at all.
Further on do not perform write operations to PRCMD and write-protected
registers by DMA transfers.
6. No special sequence is required for reading the PSC register.
Caution If a wake-up event occurs within the 5 "nop" instructions after a power save
mode request (PSC.STP = 1) the microcontroller is immediately returning from
power save mode, but may have not at all or only partly entered the power
save mode. Following three situations can occur:
1. power save mode request not accepted
wake-up configuration not established, PLL/SSCG are operating
2. power save mode request accepted, but not completed
wake-up configuration established, but PLL/SSCG operating
3. power save mode request accepted and completed
wake-up configuration established, PLL/SSCG stopped

4.3.4 CPU operation after power save mode release

The clock for the CPU system can be switched only once after reset or power
configuration save mode release.
The clocks for the Watchdog Timer, Watch Timer, and LCD Controller/Driver
can be switched only once after system reset.
Access to peripherals that have no clock supply in Sub-WATCH mode may
cause system deadlock. This can happen if the main oscillator remains
disabled.
Wake-up Wake-up configuration established means that all registers and clock paths are
configuration set to their wake-up state.
The software should check after wake-up whether the expected wake-up
configuration has been completely established. This can be achieved by
observing
• following clock generator registers, which are modified by power save mode
entry and wake-up
– after WATCH, Sub-WATCH, STOP wake-up following bits are cleared:
CKC.PLLEN, CKC.SCEN, CKC.PERIC, SCC.SEL, ICC.SEL
– after IDLE or STOP wake-up following bits are cleared:
PCC.CLS, PCC.CKS
– after Sub-WATCH or WATCH wake-up
PCC.CLS/PCC.CKS = 000
PCC.CLS/PCC.CKS = 100
• the "completed power save mode" bit CGSTAT.CMPLPSM
– CGSTAT.CMPLPSM = 0 if a power save mode request has been
accepted but not completed, wake-up configuration established, but PLL/
Preliminary User's Manual U17566EE1V2UM00
, if PSM.OSCDIS = 0
B
, if PSM.OSCDIS = 1
B
Chapter 4
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