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Bus and Memory Control (BCU, MEMC)
15
BC71 BC70 BC61 BC60 BC51 BC50 BC41 BC40 BC31 BC30 BC21 BC20 BC11 BC10 BC01 BC00
CS7
Bit position
15 to 0
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BCC - Bus cycle control register
The 16-bit BCC register controls the number of idle states inserted after the T2
cycle. Each chip select area is controlled separately. A maximum of three idle
states is possible.
Idle states can be inserted when accessing SRAM , external I/O, external
ROM, or page ROM.
Access
This register can be read/written in 16-bit units.
Address
FFFF F488
H
Initial Value
FFFF
. After system reset, three idle states are inserted.
H
14
13
12
11
10
CS6
CS5
Table 7-22
BCC register contents
Bit name
Function
BCk[1:0]
Sets the number of idle states for each chip select area.
Note
For access to internal memory, no idle states are inserted.
Caution
To initialize an external memory area after a reset, this register has to be set.
Do not access external devices before initialization is finished. Do not change
this register while an external device is accessed.
Preliminary User's Manual U17566EE1V2UM00
9
8
7
6
5
CS4
CS3
BCk[1:0]
Inserted idle states
No idle state inserted
00
B
1 idle state
01
B
2 idle states
10
B
3 idle states
11
B
Chapter 7
4
3
2
1
CS2
CS1
CS0
0
275
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