Uart Reception - NEC V850E/Dx3 Preliminary User's Manual

Chapter 16
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16.5.7 UART reception

The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and
then setting the UAnCTL0.UAnRXE bit to 1. In the reception wait status, the
RXDAn pin is monitored and start bit detection is performed.
Start bit detection is performed using a two-step detection routine.
First the rising edge of the RXDAn pin is detected and sampling is started at
the falling edge. The start bit is recognized if the RXDAn pin is low level at the
start bit sampling point. After a start bit has been recognized, the receive
operation starts, and serial data is saved to the UARTAn receive shift register
according to the set baud rate.
When the reception complete interrupt request signal (INTUAnR) is output
upon reception of the stop bit, the data of the UARTAn receive shift register is
written to the UAnRX register. However, if an overrun error (UAnSTR.UAnOVE
bit) occurs, the receive data at this time is not written to the UAnRX register
and is discarded.
Even if a parity error (UAnSTR.UAnPE bit) or a framing error (UAnSTR.UAnFE
bit) occurs during reception, reception continues until the reception position of
the first stop bit, and INTUAnR is output following reception completion.
Start
D0
bit
INTUAnR
UAnRX
Figure 16-8 UART reception
Preliminary User's Manual U17566EE1V2UM00
Asynchronous Serial Interface (UARTA)
D1 D2 D3 D4 D5 D6
Parity
Stop
D7
bit
bit