NEC V850E/Dx3 Preliminary User's Manual page 422

Chapter 11
TPnCTL0
TPnCTL1
422
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(1) Register setting in pulse width measurement mode
(a) TMPn control register 0 (TPnCTL0)
TPnCE
0/1 0 0
Note Setting is invalid when the TPnEEE bit = 1.
(b) TMPn control register 1 (TPnCTL1)
TPnEST TPnEEE
0 0 0/1
(c) TMPn I/O control register 1 (TPnIOC1)
TPnIOC1 0 0
Preliminary User's Manual U17566EE1V2UM00
TPnCKS2 TPnCKS1 TPnCKS0
0 0 0/1
TPnMD2 TPnMD1 TPnMD0
0 0 1 1
TPnIS3 TPnIS2
0 0 0/1 0/1
16-bit Timer/Event Counter P (TMP)
0/1 0/1
Select count clock
0: Stop counting
1: Enable counting
0
1, 1, 0:
Pulse width measurement mode
0: Operate with count
clock selected by
TPnCKS0 to TPnCKS2 bits
1: Count external event
count input signal
TPnIS1 TPnIS0
0/1 0/1
Select valid edge
of TIPn0 pin input
Select valid edge
of TIPn1 pin input
Note