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Chapter 13
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(2)
Compare operation (free run)
Basic settings (m = 1 to 4):
Bit
CCSGn0
CCSGn5
SWFGnm
CCSGnm
TBGnm
(a) Example: Interval timer (free run)
Setting method interval timer:
(1)
An usable compare register is one of GCCn1 to GCCn4, and the
corresponding counter (TMGn0 or TMGn1) must be selected with the
TBGnm bit.
(2)
Select a count clock cycle with the CSE12 to CSE10 bits (TMGn1
register) or CSE02 to CSE00 bits (TMGn0 register).
(3)
Write data to GCCnm.
(4)
Start timer operation by setting POWERn and TMGn0E (or TMGn1E).
Compare Operation:
(1)
When the value of the counter matches the value of GCCnm (m = 0 to 4),
a match interrupt (INTCCGnm) is output.
(2)
When the counter overflows, an overflow interrupt (INTTMGn0/
INTTMGn1) is generated.
ENFG0
FFFFH
Ma tch
TM G n0
GCCn1
INTTGnCC1
INTTGnOV0
Figure 13-6
Timing of compare mode (free run)
Data N is set in GCCn1, and the counter TMGn0 is selected.
Preliminary User's Manual U17566EE1V2UM00
16-bit Multi-Purpose Timer G (TMG)
Value
0
0
0
1
X
FFFFH
FFFFH
N
Remark
free run mode
disable TOGnm
Compare mode for
GCCnm
assign counter
for GCCnm
0: TMGn0
1: TMGn1
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