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16-bit Multi-Purpose Timer G (TMG)
Chapter 13
If only one overflow is necessary, the CCFGny bits (y = 0 to 5) can be used for
overflow detection.
Only the overflow of the TMGn0 or TMGn1counter clears the CCFGny bit
(TMGSTn register). The software-based clearing via CLRGn0 or CLRGn1 bit
(TMGMLn register) doesn't affect these bits.
The CCFGny bit is set if a TMGn0 (TMGn1) overflow occurs. This flag is only
updated if the corresponding GCCny register was read, so first read the
GCCny register and then read this flag if necessary.
(4)
Timing
The delay of each timer output TOGnm (m = 1 to 4) varies according to the
setting of the count clock with the CSEx2 to CSEx0 bits (x = 0, 1).
In capture operation 3 to 4 periods of the count-clock (f
) signal are
COUNT
required from the TIGny pin (y = 0 to 5) until a capture interrupt is output.
When TMGxE (x = 0, 1) is set earlier or simultaneously with POWERn bit, than
the Timer Gn needs 7 peripheral clocks periods (f
) to start counting.
SPCLK0
When TMGxE (x = 0, 1) is set later than POWERn bit, than the Timer Gn
needs 4 peripheral clocks periods (f
) to start counting.
SPCLK0
When a capture register (GCCny) is read, the capturing is disable during read
operation. This is intended to prevent undefined data during reading. So, if a
contention occurs between an external trigger signal and the read operation,
capture operation may be cancelled, and old data may be read.
GCCnm register (m = 1 to 4) in Compare mode:
After setting the POWERn bit you have to wait for 10 peripheral clocks periods
(f
) to perform write access to the GCCnm register (m = 1 to 4).
SPCLK0
To perform successive write access during operation, for rewriting the GCCnm
register, you have to wait for minimum 7f peripheral clocks periods (f
).
SPCLK0
Preliminary User's Manual U17566EE1V2UM00
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