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Chapter 11
TPnCTL0
TPnCTL1
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When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from
FFFFH to 0000H. The counter counts each time the valid edge of external
event count input is detected. Additionally, the set value of the TPnCCR0
register is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0
buffer register, the 16-bit counter is cleared to 0000H, and a compare match
interrupt request signal (INTTPnCC0) is generated.
The INTTPnCC0 signal is generated each time the valid edge of the external
event count input has been detected (set value of TPnCCR0 register + 1)
times.
(1)
Register setting for operation in external event count mode
(a) TMPn control register 0 (TPnCTL0)
TPnCE
0/1
0
0
(b) TMPn control register 1 (TPnCTL1)
TPnEST
TPnEEE
0
0
1
0
Preliminary User's Manual U17566EE1V2UM00
16-bit Timer/Event Counter P (TMP)
TPnCKS2 TPnCKS1 TPnCKS0
0
0
0
0
TPnMD2 TPnMD1 TPnMD0
0
0
0
0
0: Stop counting
1: Enable counting
1
0, 0, 1:
External event count mode
1: Count with external
event input signal
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