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NEC V850ES/KG2 User Manual

32-bit single-chip microcontrollers

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User's Manual

V850ES/KG2

32-bit Single-Chip Microcontrollers

Hardware

μ

PD70F3731

μ

PD70F3732

Document No. U17703EJ2V0UD00 (2nd edition)

Date Published October 2006 N CP(K)

Printed in Japan

2005

Table of Contents

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Summary of Contents for NEC V850ES/KG2

Page 1 User’s Manual V850ES/KG2 32-bit Single-Chip Microcontrollers Hardware μ PD70F3731 μ PD70F3732 Document No. U17703EJ2V0UD00 (2nd edition) Date Published October 2006 N CP(K) 2005 Printed in Japan...
Page 2 [MEMO] User’s Manual U17703EJ2V0UD...
Page 3: Notes For Cmos Devices
NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 Technology, Inc. IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany. MINICUBE is a trademark of NEC Electronics Corporation Germany or a trademark in the United States. EEPROM is a trademark of NEC Electronics Corporation Applilet is a registered trademark of NEC Electronics in Japan, Germany, Hong Kong, the People’s Republic of China, the Republic of Korea, the United Kingdom, and the United States of America.
Page 5 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 6 PREFACE Readers This manual is intended for users who wish to understand the functions of the V850ES/KG2 and design application systems using the V850ES/KG2. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/KG2 shown in the Organization below.
Page 7 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the bottom Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark:...
Page 8: Related Documents
Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/KG2 Document Name Document No. V850ES Architecture User’s Manual U15943E V850ES/KG2 Hardware User’s Manual This manual Documents related to development tools (user’s manuals)
Page 9: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION .........................19 1.1 V850ES/Kx2 Product Lineup......................19 1.2 Features ............................20 1.3 Applications............................ 22 1.4 Ordering Information ........................22 1.5 Pin Configuration (Top View)......................23 1.6 Function Block Configuration ...................... 26 1.7 Overview of Functions ........................30 CHAPTER 2 PIN FUNCTIONS ........................31 2.1 List of Pin Functions ........................
Page 10 4.3.9 Port CS............................120 4.3.10 Port CT ............................122 4.3.11 Port DH............................124 4.3.12 Port DL ............................126 4.4 Block Diagrams ..........................129 4.5 Port Register Setting When Alternate Function Is Used............154 4.6 Cautions ............................161 4.6.1 Cautions on bit manipulation instruction for port n register (Pn) ............161 4.6.2 Hysteresis characteristics........................
Page 11 6.5.3 Usage...............................200 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) ..............201 7.1 Overview ............................201 7.2 Functions ............................201 7.3 Configuration..........................202 7.4 Registers............................204 7.5 Operation ............................215 7.5.1 Interval timer mode (TP0MD2 to TP0MD0 bits = 000) ..............216 7.5.2 External event count mode (TP0MD2 to TP0MD0 bits = 001) ............226 7.5.3 External trigger pulse output mode (TP0MD2 to TP0MD0 bits = 010) ..........234 7.5.4 One-shot pulse output mode (TP0MD2 to TP0MD0 bits = 011)............246 7.5.5 PWM output mode (TP0MD2 to TP0MD0 bits = 100) ..............253...
Page 12 9.4.6 Operation as external event counter (16 bits).................. 379 9.4.7 Square-wave output operation (16-bit resolution)................380 9.4.8 Cautions ............................381 CHAPTER 10 8-BIT TIMER H ......................382 10.1 Functions ............................ 382 10.2 Configuration..........................382 10.3 Registers ............................. 385 10.4 Operation ............................ 389 10.4.1 Operation as interval timer/square wave output ................
Page 13 CHAPTER 14 A/D CONVERTER ......................434 14.1 Overview ............................. 434 14.2 Functions ............................ 434 14.3 Configuration..........................435 14.4 Registers............................. 437 14.5 Operation ............................ 445 14.5.1 Basic operation ..........................445 14.5.2 Trigger modes ..........................446 14.5.3 Operation modes..........................447 14.5.4 Power fail detection function ......................450 14.5.5 Setting method ..........................451 14.6 Cautions............................
Page 14 17.1 Features ............................498 17.2 Configuration..........................499 17.3 Registers ............................. 502 17.4 Operation ............................ 511 17.4.1 Transmission/reception completion interrupt request signal (INTCSI0n)........511 17.4.2 Single transfer mode ........................513 17.4.3 Continuous transfer mode ......................516 17.5 Output Pins ..........................524 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION ................
Page 15 19.13.2 When communication reservation function is disabled (IICF0.IICRSV0 bit = 1)......615 19.14 Cautions............................ 616 19.15 Communication Operations....................617 19.15.1 Master operation in single master system..................618 19.15.2 Master operation in multimaster system..................619 19.15.3 Slave operation ..........................622 19.16 Timing of Data Communication....................625 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) ..............632 20.1 Features ............................
Page 16 21.6.1 Illegal opcode ..........................688 21.6.2 Debug trap............................. 690 21.7 Multiple Interrupt Servicing Control..................692 21.8 Interrupt Response Time ......................694 21.9 Periods in Which Interrupts Are Not Acknowledged by CPU..........695 21.10 Cautions ............................ 695 CHAPTER 22 KEY INTERRUPT FUNCTION ..................696 22.1 Function ............................
Page 17 26.4.2 Communication mode ........................732 26.4.3 Flash memory control........................739 26.4.4 Selection of communication mode ....................740 26.4.5 Communication commands......................741 26.4.6 Pin connection..........................742 26.5 Rewriting by Self Programming ....................747 26.5.1 Overview ............................747 26.5.2 Features............................748 26.5.3 Standard self programming flow.....................749 26.5.4 Flash functions ..........................750 26.5.5 Pin processing..........................750 26.5.6 Internal resources used........................751 CHAPTER 27 ON-CHIP DEBUG FUNCTION ..................752...
Page 18 APPENDIX C REGISTER INDEX ......................836 <R> APPENDIX D LIST OF CAUTIONS ..................... 845 <R> APPENDIX E REVISION HISTORY...................... 884 E.1 Major Revisions in This Edition ....................884 User’s Manual U17703EJ2V0UD...
Page 19: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION 1.1 V850ES/Kx2 Product Lineup Product Name V850ES/KE2 V850ES/KF2 V850ES/KG2 V850ES/KJ2 Number of pins 64 pins 80 pins 100 pins 144 pins Internal memory Flash memory (KB) Supply voltage 2.7 to 5.5 V Minimum instruction execution time 50 ns @20 MHz...
Page 20: Features
CHAPTER 1 INTRODUCTION 1.2 Features Minimum instruction execution time: 50 ns (operation at main clock (f ) = 20 MHz) General-purpose registers: 32 bits × 32 registers Signed multiplication (16 × 16 → 32): 1 to 2 clocks CPU features: (Instructions without creating register hazards can be continuously executed in parallel) Saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock...
Page 21 CHAPTER 1 INTRODUCTION Serial interface Asynchronous serial interface (UART): 3 channels 3-wire serial I/O (CSI0): 2 channels 3-wire serial I/O (with automatic transmit/receive function) (CSIA): 2 channels C bus interface (I 1 channel A/D converter: 10-bit resolution × 8 channels D/A converter: 8-bit resolution ×...
Page 22: Applications
CHAPTER 1 INTRODUCTION 1.3 Applications Home audio AV equipment PC peripheral devices (keyboards, etc.) Household appliances • Outdoor units of air conditioners • Microwave ovens, rice cookers Industrial devices • Pumps • Vending machines • FA 1.4 Ordering Information Part Number Package μ...
Page 23: Pin Configuration (Top View)
CHAPTER 1 INTRODUCTION 1.5 Pin Configuration (Top View) 100-pin plastic LQFP (fine pitch) (14 × 14) μ PD70F3731GC-8EA-A μ PD70F3732GC-8EA-A PDL4/AD4 REF0 PDL3/AD3 P10/ANO0 PDL2/AD2 PDL1/AD1 P11/ANO1 PDL0/AD0 REF1 P00/TOH0 P01/TOH1 Note 1 FLMD0 PCT6/ASTB PCT4/RD Note 2 REGC PCT1/WR1 PCT0/WR0 PCM3/HLDRQ PCM2/HLDAK...
Page 24 CHAPTER 1 INTRODUCTION 100-pin plastic QFP (14 × 20) μ PD70F3731GF-JBT-A μ PD70F3732GF-JBT-A P71/ANI1 PDL7/AD7 P70/ANI0 PDL6/AD6 PDL5/AD5/FLMD1 REF0 PDL4/AD4 P10/ANO0 PDL3/AD3 P11/ANO1 PDL2/AD2 PDL1/AD1 REF1 P00/TOH0 PDL0/AD0 P01/TOH1 Note 1 FLMD0 PCT6/ASTB Note 2 REGC PCT4/RD PCT1/WR1 PCT0/WR0 PCM3/HLDRQ RESET PCM2/HLDAK PCM1/CLKOUT...
Page 25 CHAPTER 1 INTRODUCTION Pin identification A0 to A21: Address bus PDL0 to PDL15: Port DL AD0 to AD15: Address/data bus Read strobe ADTRG: A/D trigger input REGC: Regulator control Analog input RESET: ANI0 to ANI7: Reset ANO0, ANO1: Analog output RTP00 to RTP05: Real-time output port ASCK0:...
Page 26: Function Block Configuration
CHAPTER 1 INTRODUCTION 1.6 Function Block Configuration (1) Internal block diagram INTC Instruction INTP0 to INTP7 Note 1 queue HLDRQ TI000, TI001, TI010, TI011, 16-bit HLDAK 32-bit barrel Multiplier TI020, TI021, TI030, TI031 timer/event 16 × 16 → 32 shifter ASTB counter 0: 4 ch TO00 to TO03...
Page 27 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) help accelerate complex processing.
Page 28 It generates a non-maskable interrupt request signal (INTWDT2) or system reset signal (WDTRES2) after an overflow occurs. Serial interface (SIO) The V850ES/KG2 includes four kinds of serial interfaces: an asynchronous serial interface (UARTn), a clocked serial interface (CSI0m), a clocked serial interface with an automatic transmit/receive function (CSIAm), and an I C bus interface (I C0), and can simultaneously use up to seven channels.
Page 29 CHAPTER 1 INTRODUCTION (o) Real-time output function This function transfers 6-bit data set beforehand to output latches upon occurrence of a timer compare register match signal. A 1-channel 6-bit data real-time output function is provided on chip. (p) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port Alternate Function 7-bit I/O...
Page 30: Overview Of Functions
CHAPTER 1 INTRODUCTION 1.7 Overview of Functions μ μ Part Number PD70F3732 PD70F3731 Internal 256 KB 128 KB memory (single-power flash memory) (single-power flash memory) High-speed RAM 16 KB 6 KB Buffer RAM 64 bytes Memory Logical space 64 MB space External memory 3 MB...
Page 31: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS The names and functions of the pins of the V850ES/KG2 are described below, divided into port pins and non-port pins. The pin I/O buffer power supplies are divided into four systems; AV , AV , BV , and EV .
Page 32 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name Pin No. Pull-up Function Alternate Function Resistor Port 4 SI00/RXD2 I/O port SO00/TXD2 Input/output can be specified in 1-bit units. SCK00 P41 and P42 can be specified as N-ch open- drain output in 1-bit units. Port 5 TI011/RTP00/KR0 I/O port...
Page 33 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Pin No. Pull-up Function Alternate Function Resistor PCM0 Port CM WAIT I/O port PCM1 CLKOUT Input/output can be specified in 1-bit units. PCM2 HLDAK PCM3 HLDRQ PCS0 Port CS I/O port PCS1 Input/output can be specified in 1-bit units. PCT0 Port CT I/O port...
Page 34: Non-Port Pins
CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/5) Pin Name Pin No. Pull-up Function Alternate Function Resistor Output Address bus for external memory P90/TXD1/KR6 (when using a separate bus) P91/RXD1/KR7 P92/TI020/TO02 P93/TI021 P94/TI030/TO03 P95/TI031 P96/TI51/TO51 P97/SI01 P98/SO01 P99/SCK01 P910/SIA1 P911/SOA1 P912/SCKA1 P913/INTP4 P914/INTP5...
Page 35 CHAPTER 2 PIN FUNCTIONS (2/5) Pin Name Pin No. Pull-up Function Alternate Function Resistor ADTRG Input A/D converter external trigger input P32/ASCK0/TO01 ANI0 Input Analog voltage input for A/D converter ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANO0 Output Analog voltage output for D/A converter ANO1 ASCK0 Input...
Page 36 CHAPTER 2 PIN FUNCTIONS (3/5) Pin Name Pin No. Pull-up Function Alternate Function Resistor INTP0 Input External interrupt request input (maskable, analog noise elimination) INTP1 INTP2 INTP3 External interrupt request input (maskable, digital + analog noise elimination) INTP4 External interrupt request input P913/A13 (maskable, analog noise elimination) INTP5...
Page 37 CHAPTER 2 PIN FUNCTIONS (4/5) Pin Name Pin No. Pull-up Function Alternate Function Resistor SCL0 Serial clock I/O for I Fixed to N-ch open-drain output SDA0 Serial transmit/receive data I/O for I Fixed to N-ch open-drain output SI00 Input Serial receive data input for CSI00 P40/RXD2 SI01 Serial receive data input for CSI01...
Page 38 CHAPTER 2 PIN FUNCTIONS (5/5) Pin Name Pin No. Pull-up Function Alternate Function Resistor TO00 Output Timer output for TM00 P33/TI000/TIP00/TOP00 P34/TI001/TIP01/TOP01 TO01 Timer output for TM01 P32/ASCK0/ADTRG P35/TI010 TO02 Timer output for TM02 P30/TXD0 P92/A2/TI020 TO03 Timer output for TM03 P31/RXD0/INTP7 P94/A4/TI030 TO50...
Page 39: Pin Status
CHAPTER 2 PIN FUNCTIONS 2.2 Pin Status The address bus becomes undefined during accesses to the internal RAM and ROM. The data bus goes into the high-impedance state without data output. The external bus control signal becomes inactive. During peripheral I/O access, the address bus outputs the addresses of the on-chip peripheral I/Os that are accessed.
Page 40: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins (1/2) Alternate Function Pin No. I/O Circuit Recommended Connection Type Input: Independently connect to EV TOH0 via a resistor. TOH1 Output: Leave open. P03 to P06 INTP0 to INTP3 18 to 21 20 to 23...
Page 41 CHAPTER 2 PIN FUNCTIONS (2/2) Alternate Function Pin No. I/O Circuit Recommended Connection Type A9/SCK01 10-F Input: Independently connect to EV via a resistor. P910 A10/SIA1 Output: Leave open. P911 A11/SOA1 10-E P912 A12/SCKA1 10-F P913 to P915 A13/INTP4 to A15/INTP6 56 to 58 58 to 60 PCM0...
Page 42: Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS 2.4 Pin I/O Circuits (1/2) Type 2 Type 9-C P-ch Comparator – N-ch (threshold voltage) REF0 Input enable Schmitt-triggered input with hysteresis characteristics Type 5-A Type 10-A Pull-up P-ch enable Pull-up P-ch enable Data Data P-ch P-ch IN/OUT IN/OUT...
Page 43 CHAPTER 2 PIN FUNCTIONS (2/2) Type 12-B Type 13-AD REF1 Pull-up P-ch enable REF1 Data IN/OUT Data P-ch Output N-ch IN/OUT disable Output N-ch disable Input Input enable enable P-ch Analog output voltage N-ch Type 13-AB Type 16 IN/OUT Feedback cut-off Data N-ch Output disable...
Page 44: Chapter 3 Cpu Functions
CHAPTER 3 CPU FUNCTIONS The CPU of the V850ES/KG2 is based on the RISC architecture and executes most instructions in one clock cycle by using 5-stage pipeline control. 3.1 Features Number of instructions: Minimum instruction execution time: 50.0 ns (@ 20 MHz operation: 4.5 to 5.5 V, REGC = V μ...
Page 45: Cpu Register Set
CHAPTER 3 CPU FUNCTIONS 3.2 CPU Register Set The CPU registers of the V850ES/KG2 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers have 32-bit width. For details, refer to the V850ES Architecture User’s Manual.
Page 46: Program Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. All of these registers can be used as a data variable or address variable.
Page 47: System Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (LDSR, STSR instructions). Table 3-2.
Page 48 CHAPTER 3 CPU FUNCTIONS (1) Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the contents of the program status word (PSW) are saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)).
Page 49 CHAPTER 3 CPU FUNCTIONS (2) NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the program status word (PSW) are saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to FEPC, except for some instructions.
Page 50: Program Status Word (Psw)
CHAPTER 3 CPU FUNCTIONS (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of LDSR instruction execution.
Page 51 CHAPTER 3 CPU FUNCTIONS (2/2) Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set (to 1) only when the OV flag is set (to 1) during saturated operation. Saturated Operation result status Flag status...
Page 52 CHAPTER 3 CPU FUNCTIONS (6) Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW.
Page 53: Operating Modes
CHAPTER 3 CPU FUNCTIONS 3.3 Operating Modes The V850ES/KG2 has the following operating modes. (1) Normal operating mode After the system has been released from the reset state, the pins related to the bus interface are set to the port mode, execution branches to the reset entry address of the internal ROM, and instruction processing is started.
Page 54: Address Space
CHAPTER 3 CPU FUNCTIONS 3.4 Address Space 3.4.1 CPU address space For instruction addressing, up to a combined total of 16 MB of external memory area and internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear address space (data space) is supported.
Page 55: Wraparound Of Cpu Address Space
CHAPTER 3 CPU FUNCTIONS 3.4.2 Wraparound of CPU address space (1) Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calculation, the higher 6 bits ignore this and remain 0.
Page 56: Memory Map
CHAPTER 3 CPU FUNCTIONS 3.4.3 Memory map The V850ES/KG2 has reserved areas as shown below. Figure 3-2. Data Memory Map (Physical Addresses) 3FFFFFFH 3FFFFFFH On-chip peripheral I/O area (4 KB) 3FFF000H (80 KB) 3FFEFFFH 3FEC000H 3FEBFFFH Internal RAM area (60 KB)
Page 57 CHAPTER 3 CPU FUNCTIONS Figure 3-3. Program Memory Map 03FFFFFFH Access-prohibited area (Program fetch disabled area) 03FFF000H 03FFEFFFH Internal RAM area (60 KB) 03FF0000H 03FEFFFFH Access-prohibited area (Program fetch disabled area) 00400000H 003FFFFFH External memory area (2 MB) 00200000H 001FFFFFH External memory area (1 MB) 00100000H...
Page 58: Areas
CHAPTER 3 CPU FUNCTIONS 3.4.4 Areas (1) Internal ROM area An area of 1 MB from 0000000H to 00FFFFFH is reserved for the internal ROM area. (a) Internal ROM (256 KB) A 256 KB area from 0000000H to 003FFFFH is provided in the following products. Addresses 0040000H to 00FFFFFH are an access-prohibited area.
Page 59 CHAPTER 3 CPU FUNCTIONS (b) Internal ROM (128 KB) A 128 KB area from 0000000H to 001FFFFH is provided in the following products. Addresses 0020000H to 00FFFFFH are an access-prohibited area. • μ PD70F3731 Figure 3-5. Internal ROM Area (128 KB) 00FFFFFH Access-prohibited area...
Page 60 CHAPTER 3 CPU FUNCTIONS (b) Internal RAM (6 KB) A 6 KB area from 3FFB000H to 3FFC7FFH is provided as physical internal RAM. Addresses 3FF0000H to 3FFAFFFH and 3FFC800H to 3FFEFFFH are an access-prohibited area. • μ PD70F3731 Figure 3-7. Internal RAM Area (6 KB) Physical address space Logical address space 3FFEFFFH...
Page 61 CHAPTER 3 CPU FUNCTIONS (3) On-chip peripheral I/O area A 4 KB area from 3FFF000H to 3FFFFFFH is reserved as the on-chip peripheral I/O area. Figure 3-8. On-Chip Peripheral I/O Area Physical address space Logical address space 3FFFFFFH FFFFFFFH On-chip peripheral I/O area (4 KB) 3FFF000H FFFF000H...
Page 62: Recommended Use Of Address Space
(2) Data space With the V850ES/KG2, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address.
Page 63 CHAPTER 3 CPU FUNCTIONS (a) Application example of wraparound If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H ±32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can be addressed by one pointer.
Page 64 CHAPTER 3 CPU FUNCTIONS Figure 3-9. Recommended Memory Map Program space Data space F F F F F F F F H On-chip peripheral I/O F F F F F 0 0 0 H F F F F E F F F H Internal RAM x F F F F F F F H F F F E C 0 0 0 H...
Page 65: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTIONS 3.4.6 Peripheral I/O registers (1/11) Address Function Register Name Symbol Operable Bit Unit After Reset √ Note FFFFF004H Port DL register 0000H √ √ Note FFFFF004H Port DL register L PDLL √ √ Note FFFFF005H Port DL register H PDLH √...
Page 66 CHAPTER 3 CPU FUNCTIONS (2/11) Address Function Register Name Symbol Operable Bit Unit After Reset √ FFFFF0C0H DMA byte count register 0 DBC0 Undefined √ FFFFF0C2H DMA byte count register 1 DBC1 Undefined √ FFFFF0C4H DMA byte count register 2 DBC2 Undefined √...
Page 67 CHAPTER 3 CPU FUNCTIONS (3/11) Address Function Register Name Symbol Operable Bit Unit After Reset √ √ FFFFF134H Interrupt control register STIC0 √ √ FFFFF136H Interrupt control register SREIC1 √ √ FFFFF138H Interrupt control register SRIC1 √ √ FFFFF13AH Interrupt control register STIC1 √...
Page 68 CHAPTER 3 CPU FUNCTIONS (4/11) Address Function Register Name Symbol Operable Bit Unit After Reset √ √ FFFFF300H Key return mode register √ √ FFFFF30AH Selector operation control register 1 SELCNT1 √ √ FFFFF318H Digital noise elimination control register √ √...
Page 69 CHAPTER 3 CPU FUNCTIONS (5/11) Address Function Register Name Symbol Operable Bit Unit After Reset √ FFFFF48AH Bus cycle control register AAAAH √ √ FFFFF580H 8-bit timer H mode register 0 TMHMD0 √ √ FFFFF581H 8-bit timer H carrier control register 0 TMCYC0 √...
Page 70 CHAPTER 3 CPU FUNCTIONS (6/11) Address Function Register Name Symbol Operable Bit Unit After Reset √ √ FFFFF619H 16-bit timer output control register 01 TOC01 √ FFFFF620H 16-bit timer counter 02 TM02 0000H √ FFFFF622H 16-bit timer capture/compare register 020 CR020 0000H √...
Page 71 CHAPTER 3 CPU FUNCTIONS (7/11) Address Function Register Name Symbol Operable Bit Unit After Reset √ FFFFFA07H Baud rate generator control register 0 BRGC0 √ √ FFFFFA10H Asynchronous serial interface mode register 1 ASIM1 √ FFFFFA12H Receive buffer register 1 RXB1 √...
Page 72 CHAPTER 3 CPU FUNCTIONS (8/11) Address Function Register Name Symbol Operable Bit Unit After Reset √ FFFFFD08H Clocked serial interface initial transmit buffer register 0 SOTBF0 0000H √ FFFFFD08H Clocked serial interface initial transmit buffer register 0L SOTBF0L √ FFFFFD0AH Serial I/O shift register 0 SIO00 √...
Page 73 CHAPTER 3 CPU FUNCTIONS (9/11) Address Function Register Name Symbol After Reset Operable Bit Unit √ FFFFFE02H CSIA0 buffer RAM 1 CSIA0B1 Undefined √ FFFFFE02H CSIA0 buffer RAM 1L CSIA0B1L Undefined √ FFFFFE03H CSIA0 buffer RAM 1H CSIA0B1H Undefined √ FFFFFE04H CSIA0 buffer RAM 2 CSIA0B2...
Page 74 CHAPTER 3 CPU FUNCTIONS (10/11) Address Function Register Name Symbol Operable Bit Unit After Reset √ FFFFFE1EH CSIA0 buffer RAM F CSIA0BF Undefined √ FFFFFE1EH CSIA0 buffer RAM FL CSIA0BFL Undefined √ FFFFFE1FH CSIA0 buffer RAM FH CSIA0BFH Undefined √ FFFFFE20H CSIA1 buffer RAM 0 CSIA1B0...
Page 75 CHAPTER 3 CPU FUNCTIONS (11/11) Address Function Register Name Symbol Operable Bit Unit After Reset √ FFFFFE3AH CSIA1 buffer RAM D CSIA1BD Undefined √ FFFFFE3AH CSIA1 buffer RAM DL CSIA1BDL Undefined √ FFFFFE3BH CSIA1 buffer RAM DH CSIA1BDH Undefined √ FFFFFE3CH CSIA1 buffer RAM E CSIA1BE...
Page 76: Special Registers
3.4.7 Special registers Special registers are registers that prevent invalid data from being written when an inadvertent program loop occurs. The V850ES/KG2 has the following three special registers. • Power save control register (PSC) • Processor clock control register (PCC) •...
Page 77 CHAPTER 3 CPU FUNCTIONS [Description Example] When using PSC register (standby mode setting) ; PSMR register setting (IDLE, STOP mode setting) ST.B r11, PSMR[r0] LD.B DCHCn[r0], r12 ; (a) DMA transfer status stored ANDI 0xfe, r12, r13 Note 1 ST.B r13, DCHCn[r0] ; (b) DMA operation stopped <1>...
Page 78 CHAPTER 3 CPU FUNCTIONS (2) Command register (PRCMD) The PRCMD register is an 8-bit register used to prevent data from being written to registers that may have a large influence on the system, possibly causing the application system to unexpectedly stop, when an inadvertent program loop occurs.
Page 79 CHAPTER 3 CPU FUNCTIONS (3) System status register (SYS) This register is allocated with status flags showing the operating state of the entire system. This register can be read or written in 8-bit or 1-bit units. After reset: 00H Address: FFFFF802H <...
Page 80: Cautions
The VSWC register controls the bus access wait time for the on-chip peripheral I/O registers. Access to the on-chip peripheral I/O register lasts 3 clocks (during no wait), but in the V850ES/KG2, waits are required according to the internal system clock frequency. Set the values shown below to the VSWC register according to the internal system clock frequency that is used.
Page 81 CHAPTER 3 CPU FUNCTIONS (2) Access to special on-chip peripheral I/O register This product has two types of internal system buses. One type is for the CPU bus and the other is for the peripheral bus to interface with low-speed peripheral hardware.
Page 82 CHAPTER 3 CPU FUNCTIONS Peripheral Function Register Name Access Watchdog timer 1 (WDT1) WDTM1 Write 1 to 5 Note <Calculation of number of waits > ) × 2/((2 + m)/f k = {(1/f )} + 1 : Main clock oscillation frequency Watchdog timer 2 (WDT2) WDTM2 Write...
Page 83 CHAPTER 3 CPU FUNCTIONS Cautions 1. If fetched from the internal ROM or internal RAM, the number of waits is as shown above. If fetched from the external memory, the number of waits may be decreased below these. The effect of the external memory access cycles varies depending on the wait settings and the like.
Page 84 CHAPTER 3 CPU FUNCTIONS (3) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1>...
Page 85: Chapter 4 Port Functions
4.2 Basic Port Configuration The V850ES/KG2 incorporates a total of 84 I/O port pins consisting of ports 0, 1, 3 to 5, 7, 9, CM, CS, CT, DH, and DL (including 8 input-only port pins). The port configuration is shown below.
Page 86: Port Configuration
CHAPTER 4 PORT FUNCTIONS 4.3 Port Configuration Table 4-2. Port Configuration Item Configuration Control registers Port n register (Pn: n = 0, 1, 3 to 5, 7, 9, CM, CS, CT, DL, DH) Port n mode register (PMn: n = 0, 1, 3 to 5, 9, CM, CS, CT, DL, DH) Port n mode control register (PMCn: n = 0, 3 to 5, 9, CM, CS, CT, DL, DH) Port n function control register (PFCn: n = 3 to 5, 9) Port n function register (PFn: n = 3 to 5, 9)
Page 87 CHAPTER 4 PORT FUNCTIONS Table 4-3. Reading to/Writing from Pn Register Setting of PMCn Register Setting of PMn Register Writing to Pn Register Reading from Pn Register Note Port mode Output mode Write to the output latch The value of the output (PMCnm bit = 0) (PMnm bit = 0) The contents of the output latch are output...
Page 88 CHAPTER 4 PORT FUNCTIONS (3) Port n mode control register (PMCn) PMCn specifies the port mode/alternate function. Each bit of the PMCn register corresponds to one pin of port n and can be specified in 1-bit units. After reset: PMCn PMCn7 PMCn6 PMCn5...
Page 89 CHAPTER 4 PORT FUNCTIONS (5) Port n function control expansion register (PFCEn) PFCEn is a register that specifies the alternate function to be used when one pin has three or more alternate functions. Each bit of the PFCEn register corresponds to one pin of port n and can be specified in 1-bit units. After reset: 00H PFCEn PFCEn7 PFCEn6...
Page 90 CHAPTER 4 PORT FUNCTIONS (7) Pull-up resistor option register (PUn) PUn is a register that specifies the connection of an on-chip pull-up resistor. Each bit of the PUn register corresponds to one pin of port n and can be specified in 1-bit units. After reset: PUn7 PUn6...
Page 91 CHAPTER 4 PORT FUNCTIONS (8) Port settings Set the ports as follows. Figure 4-1. Register Settings and Pin Functions Port mode Output mode “0” PMn register Input mode “1” Alternate function (when two alternate functions are available) “0” Alternate function 1 “0”...
Page 92: Port 0
CHAPTER 4 PORT FUNCTIONS 4.3.1 Port 0 Port 0 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate functions. Table 4-4. Alternate-Function Pins of Port 0 Note Pin No. Pin Name Alternate Function PULL...
Page 93 CHAPTER 4 PORT FUNCTIONS (1) Port 0 register (P0) After reset: 00H (output latch) Address: FFFFF400H Control of output data (in output mode) (n = 0 to 6) 0 is output 1 is output (2) Port 0 mode register (PM0) After reset: FFH Address: FFFFF420H PM06...
Page 94 CHAPTER 4 PORT FUNCTIONS (3) Port 0 mode control register (PMC0) After reset: 00H Address: FFFFF440H PMC0 PMC06 PMC04 PMC03 PMC02 PMC01 PMC00 PMC05 PMC06 Specification of P06 pin operation mode I/O port INTP3 input PMC05 Specification of P05 pin operation mode I/O port INTP2 input PMC04...
Page 95: Port 1
CHAPTER 4 PORT FUNCTIONS 4.3.2 Port 1 Port 1 is a 2-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate functions. Table 4-5. Alternate-Function Pins of Port 1 Note Pin No. Pin Name Alternate Function PULL...
Page 96 CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option register 1 (PU1) After reset: 00H Address: FFFFFC42H PU11 PU10 PU1n Control of on-chip pull-up resistor connection (n = 0, 1) Not connected Connected User’s Manual U17703EJ2V0UD...
Page 97: Port 3
CHAPTER 4 PORT FUNCTIONS 4.3.3 Port 3 Port 3 is a 10-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate functions. Table 4-6. Alternate-Function Pins of Port 3 Note Pin No. Pin Name Alternate Function PULL...
Page 98 CHAPTER 4 PORT FUNCTIONS (1) Port 3 register (P3) After reset: 00H (output latch) Address: P3 FFFFF406H, P3L FFFFF406H, P3H FFFFF407H Note P3 (P3H (P3L) Control of output data (in output mode) (n = 0 to 9) 0 is output 1 is output Note When reading from or writing to bits 8 to 15 of the P3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the P3H register.
Page 99 CHAPTER 4 PORT FUNCTIONS (3) Port 3 mode control register (PMC3) After reset: 0000H Address: PMC3 FFFFF446H, PMC3L FFFFF446H, PMC3H FFFFF447H Note PMC3 (PMC3H PMC39 PMC38 (PMC3L) PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PMC39 Specification of P39 pin operation mode I/O port SCL0 I/O PMC38...
Page 100 CHAPTER 4 PORT FUNCTIONS (4) Port 3 function register H (PF3H) After reset: 00H Address: FFFFFC67H PF3H PF39 PF38 PF3n Specification of normal port/alternate function (n = 8, 9) When used as normal port (N-ch open-drain output) When used as alternate-function (N-ch open-drain output) Caution When using P38 and P39 as N-ch open-drain-output alternate-function pins, set in the following sequence.
Page 101 CHAPTER 4 PORT FUNCTIONS (7) Specifying alternate-function pins of port 3 PFC35 Specification of Alternate-Function Pin of P35 Pin TI010 input TO01 output PFCE34 PFC34 Specification of Alternate-Function Pin of P34 Pin TI001 input TO00 output TIP01 input TOP01 output PFCE33 PFC33 Specification of Alternate-Function Pin of P33 Pin...
Page 102 CHAPTER 4 PORT FUNCTIONS (8) Pull-up resistor option register 3 (PU3) After reset: 00H Address: FFFFFC46H PU35 PU34 PU33 PU32 PU31 PU30 PU3n Control of on-chip pull-up resistor connection (n = 0 to 5) Not connected Connected User’s Manual U17703EJ2V0UD...
Page 103: Port 4
CHAPTER 4 PORT FUNCTIONS 4.3.4 Port 4 Port 4 is a 3-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 4 includes the following alternate functions. Table 4-7. Alternate-Function Pins of Port 4 Note Pin No. Pin Name Alternate Function PULL...
Page 104 CHAPTER 4 PORT FUNCTIONS (3) Port 4 mode control register (PMC4) After reset: 00H Address: FFFFF448H PMC4 PMC42 PMC41 PMC40 PMC42 Specification of P42 pin operation mode I/O port SCK00 I/O PMC41 Specification of P41 pin operation mode I/O port SO00 output/TXD2 output PMC40 Specification of P40 pin operation mode...
Page 105 CHAPTER 4 PORT FUNCTIONS (5) Port 4 function register (PF4) After reset: 00H Address: FFFFFC68H PF42 PF41 PF4n Control of normal output/N-ch open-drain output (n = 1, 2) Normal output N-ch open-drain output Caution When using P41 and P42 as N-ch open-drain-output alternate-function pins, set in the following sequence.
Page 106: Port 5
CHAPTER 4 PORT FUNCTIONS 4.3.5 Port 5 Port 5 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 5 includes the following alternate functions. Table 4-8. Alternate-Function Pins of Port 5 Note Pin No. Pin Name Alternate Function PULL...
Page 107 CHAPTER 4 PORT FUNCTIONS (3) Port 5 mode control register (PMC5) After reset: 00H Address: FFFFF44AH PMC5 PMC55 PMC54 PMC53 PMC52 PMC51 PMC50 PMC55 Specification of P55 pin operation mode I/O port/KR5 input SCKA0 I/O/RTP05 output PMC54 Specification of P54 pin operation mode I/O port/KR4 input SOA0 output/RTP04 output PMC53...
Page 108 CHAPTER 4 PORT FUNCTIONS (5) Port 5 function control register (PFC5) After reset: 00H Address: FFFFF46AH PFC5 PFC55 PFC54 PFC53 PFC52 PFC51 PFC50 PFC55 Specification of alternate-function pin of P55 pin SCKA0 I/O RTP05 output PFC54 Specification of alternate-function pin of P54 pin SOA0 output RTP04 output PFC53...
Page 109: Port 7
CHAPTER 4 PORT FUNCTIONS 4.3.6 Port 7 Port 7 is an 8-bit input-only port for which all the pins are fixed to input. Port 7 includes the following alternate functions. Table 4-9. Alternate-Function Pins of Port 7 Note Pin No. Pin Name Alternate Function PULL...
Page 110: Port 9
CHAPTER 4 PORT FUNCTIONS 4.3.7 Port 9 Port 9 is a 16-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate functions. Table 4-10. Alternate-Function Pins of Port 9 Note Pin No. Pin Name Alternate Function PULL...
Page 111 CHAPTER 4 PORT FUNCTIONS (1) Port 9 register (P9) After reset: 00H (output latch) Address: P9 FFFFF412H, P9L FFFFF412H, P9H FFFFF413H Note P9 (P9H P915 P914 P913 P912 P911 P910 (P9L) Control of output data (in output mode) (n = 0 to 15) 0 is output 1 is output Note When reading from or writing to bits 8 to 15 of the P9 register in 8-bit or 1-bit units,...
Page 112 CHAPTER 4 PORT FUNCTIONS (1/2) After reset: 0000H Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H Note PMC9 (PMC9H PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 PMC99 PMC98 PMC97 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91 PMC90 (PMC9L) PMC915 Specification of P915 pin operation mode I/O port A15 output/INTP6 input PMC914...
Page 113 CHAPTER 4 PORT FUNCTIONS (2/2) PMC97 Specification of P97 pin operation mode I/O port A7 output/SI01 input PMC96 Specification of P96 pin operation mode I/O port/TI51 input A6 output/TO51 output PMC95 Specification of P95 pin operation mode I/O port A5 output/TI031 input PMC94 Specification of P94 pin operation mode I/O port/TI030 input...
Page 114 CHAPTER 4 PORT FUNCTIONS (4) Port 9 function register H (PF9H) After reset: 00H Address: FFFFFC73H PF9H PF912 PF911 PF99 PF98 PF9n Control of normal output/N-ch open-drain output (n = 0, 1, 3, 4) Normal output N-ch open-drain output Caution When using P98, P99, P911, and P912 as N-ch open-drain-output alternate- function pins, set in the following sequence.
Page 115 CHAPTER 4 PORT FUNCTIONS (1/2) After reset: 0000H Address: PFC9 FFFFF472H, PFC9L FFFFF472H, PFC9H FFFFF473H Note PFC9 (PFC9H PFC915 PFC914 PFC913 PFC912 PFC911 PFC910 PFC99 PFC98 (PFC9L) PFC97 PFC96 PFC95 PFC94 PFC93 PFC92 PFC91 PFC90 PFC915 Specification of alternate-function pin of P915 pin A15 output INTP6 input PFC914...
Page 116 CHAPTER 4 PORT FUNCTIONS (2/2) PFC97 Specification of alternate-function pin of P97 pin A7 output SI01 input PFC96 Specification of alternate-function pin of P96 pin A6 output TO51 output PFC95 Specification of alternate-function pin of P95 pin A5 output TI031 input PFC94 Specification of alternate-function pin of P94 pin A4 output...
Page 117 CHAPTER 4 PORT FUNCTIONS (6) Pull-up resistor option register 9 (PU9) After reset: 0000H Address: PU9 FFFFFC52H, PU9L FFFFFC52H, PU9H FFFFFC53H Note PU9 (PU9H PU915 PU914 PU913 PU912 PU911 PU910 PU99 PU98 (PU9L) PU97 PU96 PU95 PU94 PU93 PU92 PU91 PU90 PU9n Control of on-chip pull-up resistor connection (n = 0 to 15)
Page 118: Port Cm
CHAPTER 4 PORT FUNCTIONS 4.3.8 Port CM Port CM is a 4-bit I/O port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate functions. Table 4-11. Alternate-Function Pins of Port CM Note Pin No. Pin Name Alternate Function PULL...
Page 119 CHAPTER 4 PORT FUNCTIONS (3) Port CM mode control register (PMCCM) After reset: 00H Address: FFFFF04CH PMCCM PMCCM3 PMCCM2 PMCCM1 PMCCM0 PMCCM3 Specification of PCM3 pin operation mode I/O port HLDRQ input PMCCM2 Specification of PCM2 pin operation mode I/O port HLDAK output PMCCM1 Specification of PCM1 pin operation mode...
Page 120: Port Cs
CHAPTER 4 PORT FUNCTIONS 4.3.9 Port CS Port CS is a 2-bit I/O port for which I/O settings can be controlled in 1-bit units. Port CS includes the following alternate functions. Table 4-12. Alternate-Function Pins of Port CS Note Pin No. Pin Name Alternate Function PULL...
Page 121 CHAPTER 4 PORT FUNCTIONS (3) Port CS mode control register (PMCCS) After reset: 00H Address: FFFFF048H PMCCS PMCCS1 PMCCS0 PMCCSn Specification of PCSn pin operation mode (n = 0, 1) I/O port CSn output (4) Pull-up resistor option register CS (PUCS) After reset: 00H Address: FFFFFF48H PUCS...
Page 122: Port Ct
CHAPTER 4 PORT FUNCTIONS 4.3.10 Port CT Port CT is a 4-bit I/O port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate functions. Table 4-13. Alternate-Function Pins of Port CT Note Pin No. Pin Name Alternate Function PULL...
Page 123 CHAPTER 4 PORT FUNCTIONS (3) Port CT mode control register (PMCCT) After reset: 00H Address: FFFFF04AH PMCCT PMCCT6 PMCCT4 PMCCT1 PMCCT0 PMCCT6 Specification of PCT6 pin operation mode I/O port ASTB output PMCCT4 Specification of PCT4 pin operation mode I/O port RD output PMCCT1 Specification of PCT1 pin operation mode...
Page 124: Port Dh
CHAPTER 4 PORT FUNCTIONS 4.3.11 Port DH Port DH is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate functions. Table 4-14. Alternate-Function Pins of Port DH Note Pin No. Pin Name Alternate Function PULL...
Page 125 CHAPTER 4 PORT FUNCTIONS (3) Port DH mode control register (PMCDH) After reset: 00H Address: FFFFF046H PMCDH PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 PMCDHn Specification of PDHn pin operation mode (n = 0 to 5) I/O port Am output (address bus output) (m = 16 to 21) Caution When specifying the port/alternate function for each bit, pay careful attention to the operation of the alternate functions.
Page 126: Port Dl
CHAPTER 4 PORT FUNCTIONS 4.3.12 Port DL Port DL is a 16-bit I/O port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate functions. Table 4-15. Alternate-Function Pins of Port DL Note Pin No. Pin Name Alternate Function PULL...
Page 127 CHAPTER 4 PORT FUNCTIONS (1) Port DL register (PDL) After reset: 00H (output latch) Address: PDL FFFFF004H, PDLL FFFFF004H, PDLH FFFFF005H Note PDL (PDLH PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 (PDLL) PDLn Control of output data (in output mode) (n = 0 to 15)
Page 128 CHAPTER 4 PORT FUNCTIONS (3) Port DL mode control register (PMCDL) After reset: 0000H Address: PMCDL FFFFF044H, PMCDLL FFFFF044H, PMCDLH FFFFF045H Note PMCDL (PMCDLH PMCDL15 PMCDL14 PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn Specification of PDLn pin operation mode (n = 0 to 15) I/O port...
Page 129: Block Diagrams
CHAPTER 4 PORT FUNCTIONS 4.4 Block Diagrams Figure 4-2. Block Diagram of Type A-A P-ch A/D input signal N-ch Figure 4-3. Block Diagram of Type C-N PMmn PORT N-ch Output latch (Pmn) P-ch Medium-voltage input buffer Address User’s Manual U17703EJ2V0UD...
Page 130 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of Type C-UA REF1 P-ch PUmn PMmn PORT Output latch (Pmn) Address DAM.DACEn bit P-ch D/A output signal N-ch User’s Manual U17703EJ2V0UD...
Page 131 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of Type D0-U Note P-ch PUmn PMCmn PMmn Output signal of PORT alternate-function 1 Output latch (Pmn) Address Note BV in the case of PCM1 and PCM2 User’s Manual U17703EJ2V0UD...
Page 132 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of Type D0-UZ P-ch PUmn Output buffer off signal PMCmn PMmn Output signal of alternate-function 1 PORT Output latch (Pmn) Address Remark Output buffer off signal: Signal that is asserted in the IDLE or STOP mode, or when the bus is held. User’s Manual U17703EJ2V0UD...
Page 133 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of Type D1-SUIL P-ch PUmn INTR Note 1 INTRmn INTF Note 1 INTFmn PMCmn PMmn PORT Output latch (Pmn) Note 2 Address Input signal of Detection of noise alternate-function 1 elimination edge Notes 1.
Page 134 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of Type D1-UH P-ch PUmn PMCmn PMmn PORT Output latch (Pmn) Address Input signal of alternate-function 1 User’s Manual U17703EJ2V0UD...
Page 135 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of Type D2-SNFH PFmn PMCmn PMmn Output signal of PORT alternate-function 1 N-ch Output latch (Pmn) Note Address Input signal of alternate-function 1 Note There are no hysteresis characteristics in the port mode. User’s Manual U17703EJ2V0UD...
Page 136 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of Type D2-SUFL P-ch PUmn PFmn Output enable signal of alternate-function 1 PMCmn PMmn Output signal of PORT alternate-function 1 P-ch Output latch (Pmn) N-ch Note Address Input signal of alternate-function 1 Note There are no hysteresis characteristics in the port mode.
Page 137 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of Type D2-ULZ P-ch PUmn Output buffer off signal Output enable signal of alternate-function 1 PMCmn PMmn Output signal of PORT alternate-function 1 Output latch (Pmn) Address Input enable signal of alternate-function 1 Input signal of alternate-function 1 Remark Output buffer off signal: Signal that is asserted in the IDLE or STOP mode, or when the bus is held.
Page 138 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of Type E00-SUFT PUmn P-ch PFmn PFCmn PMCmn PMmn Output signal of alternate-function 2 Output signal of PORT P-ch alternate-function 1 Output latch (Pmn) N-ch Address Alternate-function input signal in port mode User’s Manual U17703EJ2V0UD...
Page 139 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of Type E00-SUT P-ch PUmn PFCmn PMCmn PMmn Output signal of alternate-function 2 Output signal of alternate-function 1 PORT Output latch (Pmn) Address Alternate-function input signal in port mode User’s Manual U17703EJ2V0UD...
Page 140 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of Type E00-SUTZ P-ch PUmn Output buffer off signal PFCmn PMCmn PMmn Output signal of alternate-function 2 Output signal of alternate-function 1 PORT Output latch (Pmn) Address Alternate-function input signal in port mode Remark Output buffer off signal: Signal that is asserted in the IDLE or STOP mode, or when the bus is held.
Page 141 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of Type E00-U P-ch PUmn PFCmn PMCmn PMmn Output signal of alternate-function 2 Output signal of PORT alternate-function 1 Output latch (Pmn) Address User’s Manual U17703EJ2V0UD...
Page 142 CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of Type E00-UF P-ch PUmn PFmn PFCmn PMCmn PMmn Output signal of alternate-function 2 Output signal of PORT P-ch alternate-function 1 Output latch (Pmn) N-ch Address User’s Manual U17703EJ2V0UD...
Page 143 CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of Type E00-UFZ PUmn P-ch PFmn Output buffer off signal PFCmn PMCmn PMmn Output signal of alternate-function 2 PORT Output signal of P-ch alternate-function 1 Output latch (Pmn) N-ch Address Remark Output buffer off signal: Signal that is asserted in the IDLE or STOP mode, or when the bus is held. User’s Manual U17703EJ2V0UD...
Page 144 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of Type E01-SUHTZ P-ch PUmn Output buffer off signal PFCmn PMCmn PMmn Output signal of PORT alternate-function 1 Output latch (Pmn) Address Input signal of alternate-function 2 Alternate-function input signal in port mode Remark Output buffer off signal: Signal that is asserted in the IDLE or STOP mode, or when the bus is held.
Page 145 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of Type E01-SUILZ PUmn P-ch INTR Note 1 INTRmn INTF Note 1 INTFmn Output buffer off signal PFCmn PMCmn PMmn Output signal of PORT alternate-function 1 Output latch (Pmn) Note 2 Address Input signal of Detection of noise alternate-function 2...
Page 146 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of Type E01-SULZ P-ch PUmn Output buffer off signal PFCmn PMCmn PMmn Output signal of PORT alternate-function 1 Output latch (Pmn) Note Address Input signal of alternate-function 2 Note There are no hysteresis characteristics in the port mode. Remark Output buffer off signal: Signal that is asserted in the IDLE or STOP mode, or when the bus is held.
Page 147 CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of Type E02-SUFLZ P-ch PUmn PFmn Output buffer off signal Output enable signal of alternate-function 2 PFCmn PMCmn PMmn Output signal of alternate-function 2 PORT Output signal of P-ch alternate-function 1 Output latch (Pmn) N-ch Note...
Page 148 CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of Type E10-SUIHL P-ch PUmn INTR Note INTRmn INTF Note INTFmn PFCmn PMCmn PMmn Output signal of alternate-function 2 PORT Output latch (Pmn) Note Address Input signal of Detection of noise alternate-function 1-2 elimination edge Input signal of alternate-function 1-1...
Page 149 CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of Type E10-SUL P-ch PUmn PFCmn PMCmn PMmn Output signal of PORT alternate-function 2 Output latch (Pmn) Note Address Input signal of alternate-function 1 Note There are no hysteresis characteristics in the port mode. User’s Manual U17703EJ2V0UD...
Page 150 CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of Type E10-SULT P-ch PUmn PFCmn PMCmn PMmn Output signal of alternate-function 2 PORT Output latch (Pmn) Address Input signal of alternate-function 1 Alternate-function input signal in port mode User’s Manual U17703EJ2V0UD...
Page 151 CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of Type E11-SULH P-ch PUmn PFCmn PMCmn PMmn PORT Output latch (Pmn) Note Address Input signal of alternate-function 1 Input signal of alternate-function 2 Note There are no hysteresis characteristics in the port mode. User’s Manual U17703EJ2V0UD...
Page 152 CHAPTER 4 PORT FUNCTIONS Figure 4-26. Block Diagram of Type E20-SUFLT P-ch PUmn PFmn PFCmn Output enable signal of alternate-function 1 PMCmn PMmn Output signal of PORT alternate-function 2 Output signal of P-ch alternate-function 1 Output latch (Pmn) N-ch Address Input signal of alternate-function 1 Alternate-function input...
Page 153 CHAPTER 4 PORT FUNCTIONS Figure 4-27. Block Diagram of Type G1010-SUL P-ch PUmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal of alternate-function 4 PORT Output signal of alternate-function 2 Output latch (Pmn) Note Address Input signal of alternate-function 1 Input signal of alternate-function 3 Note There are no hysteresis characteristics in the port mode.
Page 154: Port Register Setting When Alternate Function Is Used
CHAPTER 4 PORT FUNCTIONS 4.5 Port Register Setting When Alternate Function Is Used Table 4-16 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to description of each pin. User’s Manual U17703EJ2V0UD...
Page 155 Table 4-16. Settings When Port Pins Are Used for Alternate Functions (1/6) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCEnx Bit of PFCnx Bit of PFCn Other Bits (Registers) PMCn Register PFCEn Register Register Function Name...
Page 156 Table 4-16. Settings When Port Pins Are Used for Alternate Functions (2/6) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits (Registers) PMCn Register PFCEn Register PFCn Register Function Name...
Page 157 Table 4-16. Settings When Port Pins Are Used for Alternate Functions (3/6) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of PFCn Register Other Bits (Registers) PMCn Register Function Name TI011 Input P50 = Setting not required...
Page 158 Table 4-16. Settings When Port Pins Are Used for Alternate Functions (4/6) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of PFCn Register Other Bits (Registers) Function Name PMCn Register PFCn Register Output P90 = Setting not required...
Page 159 Table 4-16. Settings When Port Pins Are Used for Alternate Functions (5/6) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) PMCn Register PFCn Register Function Name P910 Output P910 = Setting not required...
Page 160 Table 4-16. Settings When Port Pins Are Used for Alternate Functions (6/6) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) PMCn Register PFCn Register Function Name PDH0 Output PDH0 = Setting not required...
Page 161: Cautions
Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A bit manipulation instruction is executed in the following order in the V850ES/KG2. <1> The Pn register is read in 8-bit units.
Page 162: Hysteresis Characteristics
CHAPTER 4 PORT FUNCTIONS 4.6.2 Hysteresis characteristics In port mode, the following ports do not have hysteresis characteristics. P02 to P06 P31 to P35, P38, P39 P40, P42 P93, P95, P97, P99, P910, P912 to P915 User’s Manual U17703EJ2V0UD...
Page 163: Chapter 5 Bus Control Function
CHAPTER 5 BUS CONTROL FUNCTION The V850ES/KG2 is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 5.1 Features 16-bit data bus Output is selectable from a multiplex bus with a minimum of 3 bus cycles and a separate bus with a minimum of...
Page 164: Bus Control Pins
CHAPTER 5 BUS CONTROL FUNCTION 5.2 Bus Control Pins The pins used to connect an external device are listed in the table below. Table 5-1. Bus Control Pins (When Multiplex Bus Selected) Bus Control Pin Alternate-Function Pin Function Register to Switch Between Port Mode/ Alternate-Function Mode AD0 to AD15 PDL0 to PDL15...
Page 165: Pin Status When Internal Rom, Internal Ram, Or On-Chip Peripheral I/O Is Accessed
Caution When a write access is performed to the internal ROM area, address, data, and control signals are activated in the same way as access to the external memory area. 5.2.2 Pin status in each operation mode For the pin status of the V850ES/KG2 in each operation mode, refer to 2.2 Pin Status. User’s Manual U17703EJ2V0UD...
Page 166: Memory Block Function
CHAPTER 5 BUS CONTROL FUNCTION 5.3 Memory Block Function The 64 MB memory space is divided into chip select areas of (lower) 2 MB and 2 MB. The programmable wait function and bus cycle operation mode for each of these chip select areas can be independently controlled. Figure 5-1.
Page 167: Chip Select Control Function
0000000H to 01FFFFFH (2 MB) 0200000H to 03FFFFFH (2 MB) 5.4 External Bus Interface Mode Control Function The V850ES/KG2 includes the following two external bus interface modes. • Multiplex bus mode • Separate bus mode These two modes can be selected by using the EXIMC register.
Page 168: Bus Access
The bus size of each external memory area selected by CSn can be set to 8 bits or 16 bits by using the BSC register. The external memory area of the V850ES/KG2 is selected by CS0 and CS1. (1) Bus size configuration register (BSC) This register can be read or written in 16-bit units.
Page 169: Access By Bus Size
CHAPTER 5 BUS CONTROL FUNCTION 5.5.3 Access by bus size The V850ES/KG2 accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to 16 bits.
Page 170 CHAPTER 5 BUS CONTROL FUNCTION (2) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Address 2n + 1 Byte data External Byte data External data bus data bus (b) 8-bit data bus width...
Page 171 CHAPTER 5 BUS CONTROL FUNCTION (3) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) First access Second access Address Address Address 2n + 1 2n + 1 2n + 2 Halfword...
Page 172 CHAPTER 5 BUS CONTROL FUNCTION (4) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Second access Address Address 4n + 1 4n + 3 4n + 2 Word data External Word data External data bus data bus...
Page 173 CHAPTER 5 BUS CONTROL FUNCTION (a) 16-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External Word data External data bus data bus...
Page 174 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Second access Third access Fourth access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External Word data External Word data...
Page 175 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Third access Fourth access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External Word data...
Page 176: Wait Function
CHAPTER 5 BUS CONTROL FUNCTION 5.6 Wait Function 5.6.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle that is executed for each CS space.
Page 177: External Wait Function
CHAPTER 5 BUS CONTROL FUNCTION 5.6.2 External wait function To synchronize an extremely slow memory, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). Access to each area of the internal ROM, internal RAM, and on-chip peripheral I/O is not subject to control by the external wait function, in the same manner as the programmable wait function.
Page 178: Relationship Between Programmable Wait And External Wait
CHAPTER 5 BUS CONTROL FUNCTION 5.6.3 Relationship between programmable wait and external wait Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WAIT pin. Programmable wait Wait control Wait via WAIT pin...
Page 179: Programmable Address Wait Function
CHAPTER 5 BUS CONTROL FUNCTION 5.6.4 Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address wait insertion is set for each chip select area (CS0 and CS1). If an address setup wait is inserted, it seems that the high-clock period of T1 state is extended by 1 clock.
Page 180: Idle State Insertion Function
CHAPTER 5 BUS CONTROL FUNCTION 5.7 Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by CSn in the multiplex address/data bus mode. In the separate bus mode, one idle state (TI) can be inserted after the T2 state.
Page 181: Bus Hold Function
CHAPTER 5 BUS CONTROL FUNCTION 5.8 Bus Hold Function 5.8.1 Functional outline The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to their alternate functions. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status).
Page 182: Bus Hold Procedure
CHAPTER 5 BUS CONTROL FUNCTION 5.8.2 Bus hold procedure The bus hold status transition procedure is shown below. <1> Low-level input to HLDRQ pin acknowledged <2> All bus cycle start requests inhibited Normal status <3> End of current bus cycle <4>...
Page 183: Bus Priority
CHAPTER 5 BUS CONTROL FUNCTION 5.9 Bus Priority Bus hold, instruction fetch (branch), instruction fetch (successive), operand data access, and DMA transfer are executed in the external bus cycle. Bus hold has the highest priority, followed by DMA transfer, operand data access, instruction fetch (branch), and instruction fetch (successive).
Page 184: Bus Timing
CHAPTER 5 BUS CONTROL FUNCTION 5.10 Bus Timing Figure 5-4. Multiplex Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT A21 to A16 ASTB CS1, CS0 WAIT AD15 to AD0 Idle state Programmable External wait wait 8-bit access Odd address Even address AD15 to AD8 Active...
Page 185 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-6. Multiplex Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT A21 to A16 ASTB CS1, CS0 WAIT AD15 to AD0 WR1, WR0 Programmable External wait wait 8-bit access Odd address Even address AD15 to AD8 Active Undefined...
Page 186 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-8. Multiplex Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access) Note Note CLKOUT HLDRQ HLDAK A23 to A16 Undefined Undefined AD15 to AD0 Undefined Undefined ASTB CS3 to CS0 1111 1111 Note This idle state (TI) does not depend on the BCC register settings. Remarks 1.
Page 187 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-9. Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT CS1, CS0 WAIT A21 to A0 AD15 to AD0 External Programmable Idle state wait wait 8-bit access Odd address Even address AD15 to AD8 Active Hi-Z AD7 to AD0...
Page 188 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-11. Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT CS1, CS0 WAIT A21 to A0 WR1, WR0 AD15 to AD0 Programmable External wait wait 8-bit access Odd address Even address AD15 to AD8 Active Undefined AD7 to AD0...
Page 189 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-13. Separate Bus Hold Timing (Bus Size: 8 Bits, Write) Note Note CLKOUT HLDRQ HLDAK A21 to A0 Undefined Undefined AD7 to AD0 WR1, WR0 CS1, CS0 Note This idle state (TI) does not depend on the BCC register settings. Remark The broken lines indicate high impedance.
Page 190: Cautions
CHAPTER 5 BUS CONTROL FUNCTION 5.11 Cautions With the external bus function, signals may not be output at the correct timing under the following conditions. <Operating conditions> Multiplex bus mode <1> CLKOUT asynchronous (2.7 V ≤ V < 4.0 V, 2.7 V ≤ BV = EV = AV <...
Page 191: Chapter 6 Clock Generation Function
CHAPTER 6 CLOCK GENERATION FUNCTION 6.1 Overview The following clock generation functions are available. Main clock oscillator <In PLL (×4) mode> • f = 8 to 20 MHz: 4.5 V ≤ V ≤ 5.5 V, REGC = V = 2 to 5 MHz (f •...
Page 192: Configuration
CHAPTER 6 CLOCK GENERATION FUNCTION 6.2 Configuration Figure 6-1. Clock Generator FRC bit Watch timer clock, Subclock watchdog timer clock oscillator /2 to f Watch timer clock Interval timer IDLE mode IDLE control MFRC IDLE mode PLLON bit CK2 to CK0 bits CLS bit, CK3 bit IDLE Main clock...
Page 193 CHAPTER 6 CLOCK GENERATION FUNCTION (1) Main clock oscillator The main clock oscillator oscillates the following frequencies (f • f = 2 to 5 MHz (REGC = V = 4.5 to 5.5 V, in PLL mode) • f = 2 to 4 MHz (REGC = V = 4.0 to 5.5 V, in PLL mode) μ...
Page 194: Registers
CHAPTER 6 CLOCK GENERATION FUNCTION 6.3 Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (refer to 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 03H.
Page 195 CHAPTER 6 CLOCK GENERATION FUNCTION (2/2) Clock selection (f /8 (default value) × Setting prohibited × × × Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being output. 2. Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit manipulation instruction, do not change the set values of the CK2 to CK0 bits.
Page 196 CHAPTER 6 CLOCK GENERATION FUNCTION (a) Example of setting main clock operation → subclock operation <1> CK3 bit ← 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following time after the CK3 bit is set until subclock operation is started.
Page 197 CHAPTER 6 CLOCK GENERATION FUNCTION (b) Example of setting subclock operation → main clock operation <1> MCK bit ← 0: Main clock starts oscillating <2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses. <3>...
Page 198: Operation
CHAPTER 6 CLOCK GENERATION FUNCTION 6.4 Operation 6.4.1 Operation of each clock The following table shows the operation status of each clock. Table 6-1. Operation Status of Each Clock Register Setting and PCC Register Operation Status CLS bit = 0, CLS bit = 1, CLS bit = 1, MCK bit = 0...
Page 199: Pll Function
CHAPTER 6 CLOCK GENERATION FUNCTION 6.5 PLL Function 6.5.1 Overview The PLL function is used to output the operating clock of the CPU and on-chip peripheral function at a frequency 4 times higher than the oscillation frequency, and select the clock-through mode. When PLL function is used: Input clock = 2 to 5 MHz (f : 8 to 20 MHz) Clock-through mode:...
Page 200: Usage
CHAPTER 6 CLOCK GENERATION FUNCTION 6.5.3 Usage (1) When PLL is used • After reset has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1). •...
Page 201: Chapter 7 16-Bit Timer/Event Counter P (Tmp)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Timer P (TMP) is a 16-bit timer/event counter. 7.1 Overview An outline of TMP0 is shown below. • Clock selection: 8 ways • Capture trigger input pins: 2 • External event count input pins: 1 •...
Page 202: Configuration
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.3 Configuration TMP0 includes the following hardware. Table 7-1. Configuration of TMP0 Item Configuration Timer register 16-bit counter Registers TMP0 capture/compare registers 0, 1 (TP0CCR0, TP0CCR1) TMP0 counter read buffer register (TP0CNT) CCR0, CCR1 buffer registers Note Timer inputs 2 (TIP00...
Page 203 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TP0CNT register. When the TP0CTL0.TP0CE bit = 0, the value of the 16-bit counter is FFFFH. If the TP0CNT register is read at this time, 0000H is read.
Page 204: Registers
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.4 Registers (1) TMP0 control register 0 (TP0CTL0) The TP0CTL0 register is an 8-bit register that controls the operation of TMP0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 205 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) TMP0 control register 1 (TP0CTL1) The TP0CTL1 register is an 8-bit register that controls the operation of TMP0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF5A1H <6>...
Page 206 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (3) TMP0 I/O control register 0 (TP0IOC0) The TP0IOC0 register is an 8-bit register that controls the timer output (TOP00, TOP01 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 207 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (4) TMP0 I/O control register 1 (TP0IOC1) The TP0IOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIP00, TIP01 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 208 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (5) TMP0 I/O control register 2 (TP0IOC2) The TP0IOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIP00 pin) and external trigger input signal (TIP00 pin). This register can be read or written in 8-bit or 1-bit units.
Page 209 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (6) TMP0 option register 0 (TP0OPT0) The TP0OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 210 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (7) TMP0 capture/compare register 0 (TP0CCR0) The TP0CCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TP0OPT0.TP0CCS0 bit.
Page 211 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TP0CCR0 register can be rewritten even when the TP0CTL0.TP0CE bit = 1. The set value of the TP0CCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTP0CC0) is generated.
Page 212 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (8) TMP0 capture/compare register 1 (TP0CCR1) The TP0CCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TP0OPT0.TP0CCS1 bit.
Page 213 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TP0CCR1 register can be rewritten even when the TP0CTL0.TP0CE bit = 1. The set value of the TP0CCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTP0CC1) is generated.
Page 214 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (9) TMP0 counter read buffer register (TP0CNT) The TP0CNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TP0CTL0.TP0CE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units.
Page 215: Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5 Operation TMP0 can perform the following operations. TP0CTL1.TP0EST Bit TIP00 Pin Capture/Compare Compare Register Operation (Software Trigger Bit) (External Trigger Input) Register Setting Write Interval timer mode Invalid Invalid Compare only Anytime write Note 1 External event count mode Invalid...
Page 216: Interval Timer Mode (Tp0Md2 To Tp0Md0 Bits = 000)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.1 Interval timer mode (TP0MD2 to TP0MD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTP0CC0) is generated at the specified interval if the TP0CTL0.TP0CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOP00 pin.
Page 217 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TP0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOP00 pin is inverted. Additionally, the set value of the TP0CCR0 register is transferred to the CCR0 buffer register.
Page 218 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-4. Register Setting for Interval Timer Mode Operation (2/2) (d) TMP0 counter read buffer register (TP0CNT) By reading the TP0CNT register, the count value of the 16-bit counter can be read. (e) TMP0 capture/compare register 0 (TP0CCR0) If the TP0CCR0 register is set to D , the interval is as follows.
Page 219 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Interval timer mode operation flow Figure 7-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register TOP00 pin output INTTP0CC0 signal <1> <2> <1> Count operation start flow START Initial setting of these registers is performed Register initial setting...
Page 220 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Interval timer mode operation timing (a) Operation if TP0CCR0 register is cleared to 0000H If the TP0CCR0 register is cleared to 0000H, the INTTP0CC0 signal is generated at each count clock, and the output of the TOP00 pin is inverted.
Page 221 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Operation if TP0CCR0 register is set to FFFFH If the TP0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTP0CC0 signal is generated and the output of the TOP00 pin is inverted.
Page 222 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Notes on rewriting TP0CCR0 register To change the value of the TP0CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TP0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 223 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Operation of TP0CCR1 register Figure 7-6. Configuration of TP0CCR1 Register TP0CCR1 register Output TOP01 pin CCR1 buffer register controller Match signal INTTP0CC1 signal Clear Count clock Output 16-bit counter TOP00 pin selection controller Match signal INTTP0CC0 signal...
Page 224 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TP0CCR1 register is less than the set value of the TP0CCR0 register, the INTTP0CC1 signal is generated once per cycle. At the same time, the output of the TOP01 pin is inverted. The TOP01 pin outputs a square wave with the same cycle as that output by the TOP00 pin.
Page 225 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TP0CCR1 register is greater than the set value of the TP0CCR0 register, the count value of the 16-bit counter does not match the value of the TP0CCR1 register. Consequently, the INTTP0CC1 signal is not generated, nor is the output of the TOP01 pin changed.
Page 226: External Event Count Mode (Tp0Md2 To Tp0Md0 Bits = 001)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.2 External event count mode (TP0MD2 to TP0MD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TP0CTL0.TP0CE bit is set to 1, and an interrupt request signal (INTTP0CC0) is generated each time the specified number of edges have been counted.
Page 227 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TP0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TP0CCR0 register is transferred to the CCR0 buffer register.
Page 228 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-11. Register Setting for Operation in External Event Count Mode (2/2) (e) TMP0 counter read buffer register (TP0CNT) The count value of the 16-bit counter can be read by reading the TP0CNT register. (f) TMP0 capture/compare register 0 (TP0CCR0) If D is set to the TP0CCR0 register, the counter is cleared and a compare match interrupt request...
Page 229 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) External event count mode operation flow Figure 7-12. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers...
Page 230 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TP0CCR0 and TP0CCR1 registers to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation enabled...
Page 231 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Notes on rewriting the TP0CCR0 register To change the value of the TP0CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TP0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 232 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Operation of TP0CCR1 register Figure 7-13. Configuration of TP0CCR1 Register TP0CCR1 register CCR1 buffer register Match signal INTTP0CC1 signal Clear Edge TIP00 pin 16-bit counter detector Match signal INTTP0CC0 signal TP0CE bit CCR0 buffer register TP0CCR0 register If the set value of the TP0CCR1 register is smaller than the set value of the TP0CCR0 register, the...
Page 233 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TP0CCR1 register is greater than the set value of the TP0CCR0 register, the INTTP0CC1 signal is not generated because the count value of the 16-bit counter and the value of the TP0CCR1 register do not match.
Page 234: External Trigger Pulse Output Mode (Tp0Md2 To Tp0Md0 Bits = 010)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.3 External trigger pulse output mode (TP0MD2 to TP0MD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the TP0CTL0.TP0CE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter P starts counting, and outputs a PWM waveform from the TOP01 pin.
Page 235 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-17. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TOP00 pin output (software trigger) TP0CCR1 register INTTP0CC1 signal TOP01 pin output Wait...
Page 236 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CKS2 TP0CKS1 TP0CKS0 TP0CTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1.
Page 237 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TMP0 I/O control register 2 (TP0IOC2) TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 Select valid edge of external trigger input Select valid edge of external event count input (e) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register.
Page 238 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in external trigger pulse output mode Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register CCR0 buffer register INTTP0CC0 signal...
Page 239 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <3> TP0CCR0, TP0CCR1 register setting change flow Only writing of the TP0CCR1 START register must be performed when the set duty factor is changed.
Page 240 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TP0CCR1 register last. Rewrite the TP0CCRa register after writing the TP0CCR1 register after the INTTP0CC0 signal is detected. FFFFH 16-bit counter 0000H...
Page 241 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) In order to transfer data from the TP0CCRa register to the CCRa buffer register, the TP0CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TP0CCR0 register and then set the active level width to the TP0CCR1 register.
Page 242 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, clear the TP0CCR1 register to 0000H. If the set value of the TP0CCR0 register is FFFFH, the INTTP0CC1 signal is generated periodically. Count clock −...
Page 243 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Conflict between trigger detection and match with TP0CCR1 register If the trigger is detected immediately after the INTTP0CC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOP01 pin is asserted, and the counter continues counting.
Page 244 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Conflict between trigger detection and match with TP0CCR0 register If the trigger is detected immediately after the INTTP0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOP01 pin is extended by time from generation of the INTTP0CC0 signal to trigger detection.
Page 245 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Generation timing of compare match interrupt request signal (INTTP0CC1) The timing of generation of the INTTP0CC1 signal in the external trigger pulse output mode differs from the timing of other INTTP0CC1 signals; the INTTP0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TP0CCR1 register.
Page 246: One-Shot Pulse Output Mode (Tp0Md2 To Tp0Md0 Bits = 011)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.4 One-shot pulse output mode (TP0MD2 to TP0MD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TP0CTL0.TP0CE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter P starts counting, and outputs a one-shot pulse from the TOP01 pin.
Page 247 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-21. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TOP00 pin output (software trigger) TP0CCR1 register INTTP0CC1 signal TOP01 pin output Delay Active...
Page 248 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-22. Setting of Registers in One-Shot Pulse Output Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CKS2 TP0CKS1 TP0CKS0 TP0CTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1. (b) TMP0 control register 1 (TP0CTL1) TP0EST TP0EEE...
Page 249 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-22. Setting of Registers in One-Shot Pulse Output Mode (2/2) (d) TMP0 I/O control register 2 (TP0IOC2) TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 Select valid edge of external trigger input Select valid edge of external event count input (e) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register.
Page 250 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in one-shot pulse output mode Figure 7-23. Software Processing Flow in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TP0CCR1 register INTTP0CC1 signal TOP01 pin output...
Page 251 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TP0CCRa register To change the set value of the TP0CCRa register to a smaller value, stop counting once, and then change the set value.
Page 252 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Generation timing of compare match interrupt request signal (INTTP0CC1) The generation timing of the INTTP0CC1 signal in the one-shot pulse output mode is different from other INTTP0CC1 signals; the INTTP0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TP0CCR1 register.
Page 253: Pwm Output Mode (Tp0Md2 To Tp0Md0 Bits = 100)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.5 PWM output mode (TP0MD2 to TP0MD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOP01 pin when the TP0CTL0.TP0CE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOP00 pin. Figure 7-24.
Page 254 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-25. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register CCR0 buffer register INTTP0CC0 signal TOP00 pin output TP0CCR1 register CCR1 buffer register INTTP0CC1 signal TOP01 pin output Active period Cycle Inactive period...
Page 255 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-26. Register Setting in PWM Output Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CKS2 TP0CKS1 TP0CKS0 TP0CTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1. (b) TMP0 control register 1 (TP0CTL1) TP0EST TP0EEE...
Page 256 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-26. Register Setting in PWM Output Mode (2/2) (d) TMP0 I/O control register 2 (TP0IOC2) TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 Select valid edge of external event count input. (e) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register.
Page 257 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in PWM output mode Figure 7-27. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register CCR0 buffer register INTTP0CC0 signal TOP00 pin output TP0CCR1 register CCR1 buffer register INTTP0CC1 signal...
Page 258 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-27. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <3> TP0CCR0, TP0CCR1 register setting change flow Only writing of the TP0CCR1 START register must be performed when the set duty factor is changed.
Page 259 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TP0CCR1 register last. Rewrite the TP0CCRa register after writing the TP0CCR1 register after the INTTP0CC1 signal is detected. FFFFH 16-bit counter 0000H...
Page 260 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TP0CCR1 register to 0000H. If the set value of the TP0CCR0 register is FFFFH, the INTTP0CC1 signal is generated periodically. Count clock −...
Page 261 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Generation timing of compare match interrupt request signal (INTTP0CC1) The timing of generation of the INTTP0CC1 signal in the PWM output mode differs from the timing of other INTTP0CC1 signals; the INTTP0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TP0CCR1 register.
Page 262: Free-Running Timer Mode (Tp0Md2 To Tp0Md0 Bits = 101)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.6 Free-running timer mode (TP0MD2 to TP0MD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter P starts counting when the TP0CTL0.TP0CE bit is set to 1. At this time, the TP0CCRa register can be used as a compare register or a capture register, depending on the setting of the TP0OPT0.TP0CCS0 and TP0OPT0.TP0CCS1 bits.
Page 263 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TP0CE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOP00 and TOP01 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TP0CCRa register, a compare match interrupt request signal (INTTP0CCa) is generated, and the output signal of the TOP0a pin is inverted.
Page 264 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TP0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIP0a pin is detected, the count value of the 16-bit counter is stored in the TP0CCRa register, and a capture interrupt request signal (INTTP0CCa) is generated.
Page 265 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-31. Register Setting in Free-Running Timer Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CKS2 TP0CKS1 TP0CKS0 TP0CTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1 (b) TMP0 control register 1 (TP0CTL1) TP0EST TP0EEE...
Page 266 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-31. Register Setting in Free-Running Timer Mode (2/2) (d) TMP0 I/O control register 1 (TP0IOC1) TP0IS3 TP0IS2 TP0IS1 TP0IS0 TP0IOC1 Select valid edge of TIP00 pin input Select valid edge of TIP01 pin input (e) TMP0 I/O control register 2 (TP0IOC2) TP0EES1 TP0EES0 TP0ETS1 TP0ETS0...
Page 267 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal TOP00 pin output...
Page 268 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TP0CTL0 register is performed before setting the (TP0CKS0 to TP0CKS2 bits) TP0CE bit to 1.
Page 269 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) When using capture/compare register as capture register Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TP0CE bit TIP00 pin input TP0CCR0 register 0000 0000 INTTP0CC0 signal TIP01 pin input 0000...
Page 270 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TP0CTL0 register is performed before setting the (TP0CKS0 to TP0CKS2 bits) TP0CE bit to 1.
Page 271 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter P is used as an interval timer with the TP0CCRa register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTP0CCa signal has been detected.
Page 272 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TP0CCRa register used as a capture register, software processing is necessary for reading the capture register each time the INTTP0CCa signal has been detected and for calculating an interval.
Page 273 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two capture registers are used FFFFH 16-bit counter...
Page 274 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TP0CE bit INTTP0OV signal TP0OVF bit Note TP0OVF0 flag TIP00 pin input TP0CCR0 register Note TP0OVF1 flag TIP01 pin input TP0CCR1 register <1>...
Page 275 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TP0CE bit INTTP0OV signal TP0OVF bit Note TP0OVF0 flag TIP00 pin input TP0CCR0 register Note TP0OVF1 flag TIP01 pin input TP0CCR1 register <1>...
Page 276 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
Page 277 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TP0CE bit TIP0a pin input TP0CCRa register INTTP0OV signal TP0OVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1>...
Page 278 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TP0OVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TP0OPT0 register. To accurately detect an overflow, read the TP0OVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
Page 279: Pulse Width Measurement Mode (Tp0Md2 To Tp0Md0 Bits = 110)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.7 Pulse width measurement mode (TP0MD2 to TP0MD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TP0CTL0.TP0CE bit is set to 1. Each time the valid edge input to the TIP0a pin has been detected, the count value of the 16-bit counter is stored in the TP0CCRa register, and the 16-bit counter is cleared to 0000H.
Page 280 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-35. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TP0CE bit TIP0a pin input 0000H TP0CCRa register INTTP0CCa signal INTTP0OV signal Cleared to 0 by TP0OVF bit CLR instruction Remark a = 0, 1 When the TP0CE bit is set to 1, the 16-bit counter starts counting.
Page 281 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-36. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CKS2 TP0CKS1 TP0CKS0 TP0CTL0 Note Select count clock 0: Stop counting 1: Enable counting Note Setting is invalid when the TP0EEE bit = 1. (b) TMP0 control register 1 (TP0CTL1) TP0EST TP0EEE...
Page 282 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-36. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMP0 option register 0 (TP0OPT0) TP0CCS1 TP0CCS0 TP0OVF TP0OPT0 Overflow flag (f) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register. (g) TMP0 capture/compare registers 0 and 1 (TP0CCR0 and TP0CCR1) These registers store the count value of the 16-bit counter when the valid edge input to the TIP0a pin is detected.
Page 283 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in pulse width measurement mode Figure 7-37. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TP0CE bit TIP00 pin input 0000H 0000H TP0CCR0 register INTTP0CC0 signal <1>...
Page 284 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TP0OVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TP0OPT0 register.
Page 285: Timer Output Operations
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.8 Timer output operations The following table shows the operations and output levels of the TOP00 and TOP01 pins. Table 7-4. Timer Output Control in Each Mode Operation Mode TOP01 Pin TOP00 Pin Interval timer mode Square wave output −...
Page 286: Eliminating Noise On Capture Trigger Input Pin (Tip0A)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6 Eliminating Noise on Capture Trigger Input Pin (TIP0a) The TIP0a pin has a digital noise eliminator. However, this circuit is valid only when the pin is used as a capture trigger input pin; it is invalid when the pin is used as an external event count input pin or external trigger input pin.
Page 287 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) <Setting procedure> <1> Select the number of times of sampling and the sampling clock by using the PaNFC register. <2> Select the alternate function (of the TIP0a pin) by using the PMC3, PFC3, and PFCE3 registers. <3>...
Page 288: Cautions
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.7 Cautions (1) Capture operation When the capture operation is used and f /8, f /16, f /32, f /64, f /128, or the external event counter (TP0CLT1.TP0EEE bit = 1) is selected as the count clock, FFFFH, not 0000H, may be captured in the TP0CCRn register if the capture trigger is input immediately after the TP0CE bit is set to 1.
Page 289: Chapter 8 16-Bit Timer/Event Counter 0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 In the V850ES/KG2, four channels of 16-bit timer/event counter 0 are provided. 8.1 Functions 16-bit timer/event counter 0n has the following functions (n = 0 to 3). (1) Interval timer 16-bit timer/event counter 0n generates an interrupt request at the preset time interval.
Page 290: Configuration
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.2 Configuration 16-bit timer/event counter 0n includes the following hardware. Table 8-1. Configuration of 16-Bit Timer/Event Counter 0n Item Configuration Time/counter 16-bit timer counter 0n (TM0n) 16-bit timer capture/compare registers: 16-bit × 2 (CR0n0, CR0n1) Register Timer input 2 (TI0n0, TI0n1 pins)
Page 291 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (1) 16-bit timer counter 0n (TM0n) The TM0n register is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. After reset: 0000H Address: TM00 FFFFF600H, TM01 FFFFF610H, TM02 FFFFF620H, TM03 FFFFF630H TM0n...
Page 292 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (i) When the CR0n0 register is used as a compare register The value set in the CR0n0 register is constantly compared with the TM0n register count value, and an interrupt request signal (INTTM0n0) is generated if they match. The value is held until the CR0n0 register is rewritten.
Page 293 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (c) Setting range when used as compare register When the CR0n0 or CR0n1 register is used as a compare register, set it as shown below. Operation CR0n0 Register CR0n1 Register 0000H < N ≤ FFFFH ≤...
Page 294 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Table 8-2. Capture Operation of CR0n0 and CR0n1 Registers External Input Signal TI0n0 Pin Input TI0n1 Pin Input Capture Operation Capture operation of CRC0n1 bit = 1 Set values of ESn01 and CRC0n1 bit = 0 Set values of ESn11 and CR0n0 register TI0n0 pin input...
Page 295: Registers
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.3 Registers Registers used to control 16-bit timer/event counter 0n are shown below. • 16-bit timer mode control register 0n (TMC0n) • Capture/compare control register 0n (CRC0n) • 16-bit timer output control register 0n (TOC0n) •...
Page 296 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 After reset: 00H Address: TMC00 FFFFF606H, TMC01 FFFFF616H, TMC02 FFFFF626H TMC03 FFFFF636H <0> TMC0n TMC0n3 TMC0n2 TMC0n1 OVF0n (n = 0 to 3) TMC0n3 TMC0n2 Enable operation of 16-bit timer/event counter 0n Disables TM0n operation. Stops supplying operating clock. Clears 16-bit timer counter (TM0n).
Page 297 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (2) Capture/compare control register 0n (CRC0n) The CRC0n register is the register that controls the operation of the CR0n0 and CR0n1 registers. Changing the value of the CRC0n register is prohibited during operation (when the TMC0n.TMC0n3 and TMC0n.TMC0n2 bits = other than 00).
Page 298 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (3) 16-bit timer output control register 0n (TOC0n) The TOC0n register is an 8-bit register that controls the TO0n pin output. The TOC0n register can be rewritten while only the OSPT0n bit is operating (when the TMC0n.TMC0n3 and TMC0n.TMC0n2 bits = other than 00).
Page 299 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (2/2) LVS0n LVR0n Setting of TO0n pin output status No change Initial value of TO0n pin output is low level (TO0n pin output is cleared to 0). Initial value of TO0n pin output is high level (TO0n pin output is set to 1). Setting prohibited •...
Page 300 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (4) Prescaler mode register 0n (PRM0n) The PRM0n register is the register that sets the TM0n register count clock and TI0n0 and TI0n1 pin input valid edges. The PRM0n1 and PRM0n0 bits are set in combination with the SELCNT1.ISEL1n bit. Refer to 8.3 (6) Count clock setting for 16-bit timer/event counter 0n for details.
Page 301 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (5) Selector operation control register 1 (SELCNT1) The SELCNT1 register sets the count clock of 16-bit timer/event counter 0n. The SELCNT1 register is set in combination with the PRM0n.PRMn01 and PRM0n.PRMn00 bits. Refer to 8.3 (6) Count clock setting for 16-bit timer/event counter 0n for details.
Page 302 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (b) Count clock for 16-bit timer/event counter 01 Note 1 SELCNT1 Register PRM01 Register Selection of Count Clock ISEL11 Bit PRM011 Bit PRM010 Bit Count Clock = 20 MHz = 16 MHz = 10 MHz Setting prohibited Setting prohibited 100 ns 200 ns...
Page 303: Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4 Operation 8.4.1 Interval timer operation If the TMC0n.TMC0n3 and TMC0n.TMC0n2 bits are set to 11 (clear & start mode entered upon a match between the TM0n register and the CR0n0 register), the count operation is started in synchronization with the count clock. When the value of the TM0n register later matches the value of the CR0n0 register, the TM0n register is cleared to 0000H and a match interrupt signal (INTTM0n0) is generated.
Page 304 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-4. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n Clears and starts on match between TM0n and CR0n0. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CR0n0 used as compare register...
Page 305 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-5. Example of Software Processing for Interval Timer Function TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Compare register (CR0n0) Compare match interrupt (INTTM0n0) <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers is performed before PRM0n register, setting the TMC0n3 and TMC0n2 bits to 11.
Page 306: Square Wave Output Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4.2 Square wave output operation When 16-bit timer/event counter 0n operates as an interval timer (see 8.4.1), a square wave can be output from the TO0n pin by setting the TOC0n register to 03H. When the TMC0n.TMC0n3 and TMC0n.TMC0n2 bits are set to 11 (count clear &...
Page 307 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-8. Example of Register Settings for Square Wave Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n Clears and starts on match between TM0n and CR0n0. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CR0n0 used as compare register...
Page 308 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-9. Example of Software Processing for Square Wave Output Function TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Compare register (CR0n0) TO0n pin output Compare match interrupt (INTTM0n0) TO0n output control bit (TOC0n1, TOE0n) <1>...
Page 309: External Event Counter Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4.3 External event counter operation When the PRM0n.PRM0n1 and PRM0n.PRM0n0 bits are set to 11 (for counting up with the valid edge of the TI0n0 pin) and the TMC0n.TMC0n3 and TMC0n.TMC0n2 bits are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between the TM0n register and the CR0n0 register (INTTM0n0) is generated.
Page 310 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-11. Example of Register Settings in External Event Counter Mode (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n Clears and starts on match between TM0n and CR0n0. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CR0n0 used as compare register...
Page 311 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-12. Example of Software Processing in External Event Counter Mode TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Compare register (CR0n0) TO0n pin output Compare match interrupt (INTTM0n0) TO0n output control bit (TOC0n4, TOC0n1, TOE0n) <1>...
Page 312: Operation In Clear & Start Mode Entered By Ti0N0 Pin Valid Edge Input
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4.4 Operation in clear & start mode entered by TI0n0 pin valid edge input When the TMC0n.TMC0n3 and TMC0n.TMC0n2 bits are set to 10 (clear & start mode entered by the TI0n0 pin valid edge input) and the count clock (set by the PRM0n, SELCNT1 registers) is supplied to the timer/event counter, the TM0n register starts counting up.
Page 313 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (1) Operation in clear & start mode entered by TI0n0 pin valid edge input (CR0n0 register: compare register, CR0n1 register: compare register) Figure 8-13. Block Diagram of Clear & Start Mode Entered by TI0n0 Pin Valid Edge Input (CR0n0 register: Compare Register, CR0n1 register: Compare Register) Edge TI0n0 pin...
Page 314 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-14. Timing Example of Clear & Start Mode Entered by TI0n0 Pin Valid Edge Input (CR0n0 Register: Compare Register, CR0n1 Register: Compare Register) (a) TOC0n = 13H, PRM0n = 10H, CRC0n = 00H, TMC0n = 08H TM0n register 0000H Operable bits...
Page 315 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (2) Operation in clear & start mode entered by TI0n0 pin valid edge input (CR0n0 register: compare register, CR0n1 register: capture register) Figure 8-15. Block Diagram of Clear & Start Mode Entered by TI0n0 Pin Valid Edge Input (CR0n0 Register: Compare Register, CR0n1 Register: Capture Register) Edge TI0n0 pin...
Page 316 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-16. Timing Example of Clear & Start Mode Entered by TI0n0 Pin Valid Edge Input (CR0n0 Register: Compare Register, CR0n1 Register: Capture Register) (1/2) (a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 08H, CR0n0 = 0000H TM0n register 0000H Operable bits...
Page 317 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-16. Timing Example of Clear & Start Mode Entered by TI0n0 Pin Valid Edge Input (CR0n0 Register: Compare Register, CR0n1 Register: Capture Register) (2/2) (b) TOC0n = 13H, PRM0n = 10H, CRC0n = 04H, TMC0n = 0AH, CR0n0 = 0003H TM0n register 0003H 0000H...
Page 318 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (3) Operation in clear & start mode entered by TI0n0 pin valid edge input (CR0n0 register: capture register, CR0n1 register: compare register) Figure 8-17. Block Diagram of Clear & Start Mode Entered by TI0n0 Pin Valid Edge Input (CR0n0 Register: Capture Register, CR0n1 Register: Compare Register) Edge TI0n0 pin...
Page 319 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-18. Timing Example of Clear & Start Mode Entered by TI0n0 Pin Valid Edge Input (CR0n0 Register: Capture Register, CR0n1 Register: Compare Register) (1/2) (a) TOC0n = 13H, PRM0n = 10H, CRC0n = 03H, TMC0n = 08H, CR0n1 = 0000H TM0n register 0000H Operable bits...
Page 320 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-18. Timing Example of Clear & Start Mode Entered by TI0n0 Pin Valid Edge Input (CR0n0 Register: Capture Register, CR0n1 Register: Compare Register) (2/2) (b) TOC0n = 13H, PRM0n = 10H, CRC0n = 03H, TMC0n = 0AH, CR0n1 = 0003H TM0n register 0003H 0000H...
Page 321 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (4) Operation in clear & start mode entered by TI0n0 pin valid edge input (CR0n0 register: capture register, CR0n1 register: capture register) Figure 8-19. Block Diagram of Clear & Start Mode Entered by TI0n0 Pin Valid Edge Input (CR0n0 Register: Capture Register, CR0n1 Register: Capture Register) Operable bits TMC0n3, TMC0n2...
Page 322 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-20. Timing Example of Clear & Start Mode Entered by TI0n0 Pin Valid Edge Input (CR0n0 Register: Capture Register, CR0n1 Register: Capture Register) (1/3) (a) TOC0n = 13H, PRM0n = 30H, CRC0n = 05H, TMC0n = 0AH TM0n register 0000H Operable bits...
Page 323 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-20. Timing Example of Clear & Start Mode Entered by TI0n0 Pin Valid Edge Input (CR0n0 Register: Capture Register, CR0n1 Register: Capture Register) (2/3) (b) TOC0n = 13H, PRM0n = C0H, CRC0n = 05H, TMC0n = 0AH FFFFH TM0n register 0000H...
Page 324 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-20. Timing Example of Clear & Start Mode Entered by TI0n0 Pin Valid Edge Input (CR0n0 Register: Capture Register, CR0n1 Register: Capture Register) (3/3) (c) TOC0n = 13H, PRM0n = 00H, CRC0n = 07H, TMC0n = 0AH TM0n register 0000H Operable bits...
Page 325 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-21. Example of Register Settings in Clear & Start Mode Entered by TI0n0 Pin Valid Edge Input (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n 0: Inverts TO0n output on match between CR0n0 and CR0n1.
Page 326 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-21. Example of Register Settings in Clear & Start Mode Entered by TI0n0 Pin Valid Edge Input (2/2) (d) Prescaler mode register 0n (PRM0n), selector operation control register 1 (SELCNT1) ESn11 ESn10 ESn01 ESn00 PRM0n1 PRM0n0 ISEL1n...
Page 327 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-22. Example of Software Processing in Clear & Start Mode Entered by TI0n0 Pin Valid Edge Input TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Count clear input (TI0n0 pin input) Compare register (CR0n0) Compare match interrupt (INTTM0n0) Compare register...
Page 328: Free-Running Timer Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4.5 Free-running timer operation When the TMC0n.TMC0n3 and TMC0n.TMC0n2 bits are set to 01 (free-running timer mode), 16-bit timer/event counter 0n continues counting up in synchronization with the count clock. When it has counted up to FFFFH, the overflow flag (TMC0n.OVF0n bit) is set to 1 at the next clock, and the TM0n register is cleared (to 0000H) and continues counting.
Page 329 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-24. Timing Example of Free-Running Timer Mode (CR0n0 Register: Compare Register, CR0n1 Register: Compare Register) • TOC0n = 13H, PRM0n = 00H, CRC0n = 00H, TMC0n = 04H FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Compare register (CR0n0)
Page 330 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-26. Timing Example of Free-Running Timer Mode (CR0n0 Register: Compare Register, CR0n1 Register: Capture Register) • TOC0n = 13H, PRM0n = 10H, CRC0n = 04H, TMC0n = 04H FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Capture trigger input (TI0n0)
Page 331 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (3) Free-running timer mode operation (CR0n0 register: capture register, CR0n1 register: capture register) Figure 8-27. Block Diagram of Free-Running Timer Mode (CR0n0 Register: Capture Register, CR0n1 Register: Capture Register) Operable bits TMC0n3, TMC0n2 16-bit counter Count clock (TM0n) Capture register...
Page 332 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-28. Timing Example of Free-Running Timer Mode (CR0n0 Register: Capture Register, CR0n1 Register: Capture Register) (1/2) (a) TOC0n = 13H, PRM0n = 0 to 50H, CRC0n = 05H, TMC0n = 04H FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2)
Page 333 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-28. Timing Example of Free-Running Timer Mode (CR0n0 Register: Capture Register, CR0n1 Register: Capture Register) (2/2) (b) TOC0n = 13H, PRM0n = C0H, CRC0n = 05H, TMC0n = 04H FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Capture trigger input...
Page 334 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-29. Example of Register Settings in Free-Running Timer Mode (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n 0: Inverts TO0n pin output on match between CR0n0 and CR0n1. 1: Inverts TO0n pin output on match between CR0n0 and CR0n1 and valid edge of TI0n0 pin.
Page 335 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-29. Example of Register Settings in Free-Running Timer Mode (2/2) (d) Prescaler mode register 0n (PRM0n), selector operation control register 1 (SELCNT1) ESn11 ESn10 ESn01 ESn00 PRM0n1 PRM0n0 ISEL1n PRM0n SELCNT1 Count clock selection (setting TI0n0 valid edge is prohibited) 00: Falling edge detection 01: Rising edge detection...
Page 336 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-30. Example of Software Processing in Free-Running Timer Mode FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Compare register (CR0n0) Compare match interrupt (INTTM0n0) Compare register (CR0n1) Compare match interrupt (INTTM0n1) Timer output control bits (TOE0n, TOC0n4, TOC0n1) TO0n pin output <1>...
Page 337: Ppg Output Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4.6 PPG output operation A rectangular wave having a pulse width set in advance by the CR0n1 register is output from the TO0n pin as a PPG (Programmable Pulse Generator) signal during a cycle set by the CR0n0 register when the TMC0n.TMC0n3 and TMC0n.TMC0n2 bits are set to 11 (clear &...
Page 338 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-32. Example of Register Settings for PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n Clears and starts on match between TM0n and CR0n0. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CR0n0 used as compare register...
Page 339 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-33. Example of Software Processing for PPG Output Operation TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Compare register (CR0n0) Compare match interrupt (INTTM0n0) Compare register (CR0n1) Compare match interrupt (INTTM0n1) Timer output control bits (TOE0n, TOC0n4, TOC0n1) TO0n pin output N + 1...
Page 340: One-Shot Pulse Output Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4.7 One-shot pulse output operation A one-shot pulse can be output by setting the TMC0n.TMC0n3 and TMC0n.TMC0n2 bits to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI0n0 pin valid edge) and setting the TOC0n.OSPE0n bit to 1. When the TOC0n.OSPT0n is set to 1 or when the valid edge is input to the TI0n0 pin during timer operation, clearing &...
Page 341 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-35. Example of Register Settings for One-Shot Pulse Output Operation (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n 01: Free running timer mode 10: Clear and start mode by valid edge of TI0n0 pin.
Page 342 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-35. Example of Register Settings for One-Shot Pulse Output Operation (2/2) (e) 16-bit timer counter 0n (TM0n) By reading the TM0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (CR0n0) This register is used as a compare register when a one-shot pulse is output.
Page 343 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-36. Example of Software Processing for One-Shot Pulse Output Operation (1/2) FFFFH TM0n register 0000H Operable bits 01 or 10 (TMC0n3, TMC0n2) One-shot pulse enable bit (OSPEn) One-shot pulse trigger bit (OSPTn) One-shot pulse trigger input (TI0n0 pin) Overflow plug (OVF0n)
Page 344 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-36. Example of Software Processing for One-Shot Pulse Output Operation (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers is performed PRM0n register, before setting the TMC0n3 and TMC0n2 bits. SELCNT1 register, CRC0n register, Note...
Page 345: Pulse Width Measurement Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4.8 Pulse width measurement operation The TM0n register can be used to measure the pulse width of the signal input to the TI0n0 and TI0n1 pins. Measurement can be accomplished by operating the 16-bit timer/event counter 0n in the free-running timer mode or by restarting the timer in synchronization with the signal input to the TI0n0 pin.
Page 346 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 A pulse width can be measured in the following three ways. • Measuring the pulse width by using two input signals of the TI0n0 and TI0n1 pins (free-running timer mode) • Measuring the pulse width by using one input signal of the TI0n0 pin (free-running timer mode) •...
Page 347 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (2) Measuring the pulse width by using one input signal of the TI0n0 pin (free-running timer mode) Set the free-running timer mode (the TMC0n.TMC0n3 and TMC0n.TMC0n2 bits = 01). The count value of the TM0n register is captured to the CR0n0 register in the phase reverse to the valid edge detected on the TI0n0 pin.
Page 348 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (3) Measuring the pulse width by using one input signal of the TI0n0 pin (clear & start mode entered by the TI0n0 pin valid edge input) Set the clear & start mode entered by the TI0n0 pin valid edge (the TMC0n.TMC0n3 and TMC0n.TMC0n2 bits = 10).
Page 349 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-42. Example of Register Settings for Pulse Width Measurement (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n 01: Free running timer mode 10: Clear and start mode entered by valid edge of TI0n0 pin.
Page 350 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-42. Example of Register Settings for Pulse Width Measurement (2/2) (e) 16-bit timer counter 0n (TM0n) By reading the TM0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (CR0n0) This register is used as a capture register.
Page 351 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-43. Example of Software Processing for Pulse Width Measurement (1/2) (a) Example of free-running timer mode FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Capture trigger input (TI0n0) Capture register 0000H (CR0n1) Capture interrupt (INTTM0n1) Capture trigger input (TI0n1)
Page 352 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-43. Example of Software Processing for Pulse Width Measurement (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers is performed PRM0n register, before setting the TMC0n3 and TMC0n2 bits. SELCNT1 register, CRC0n register, port setting...
Page 353: Special Use Of Tm0N
8.5.1 Rewriting CR0n1 register during TM0n operation In principle, rewriting the CR0n0 and CR0n1 registers of the V850ES/KG2 when they are used as compare registers is prohibited while the TM0n register is operating (TMC0n.TMC0n3 and TMC0n.TMC0n2 bits = other than 00).
Page 354 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (2) Setting the LVS0n and LVR0n bits Set the LVS0n and LVR0n bits using the following procedure. Figure 8-44. Example of Flow for Setting LVS0n and LVR0n Bits Setting TOC0n.OSPE0n, TOC0n4, TOC0n1 bits <1> Setting of timer output operation Setting TOC0n.TOE0n Setting...
Page 355: Cautions
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.6 Cautions (1) Alternate functions of TI0n0/TO0n pins Channel Alternate function Remarks TM00 TI000 P33/TO00/TIP00/TOP00 Shares the pin with TO00. TI001 P34/TO00/TIP01/TOP01 Shares the pin with TO00. TO00 P33/TI000/TIP00/TOP00 Assigned to two pins, P33 and P34. P34/TI001/TIP01/TOP01 TM01 TI010...
Page 356 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (b) For TM01 • To perform the one-shot pulse output with detecting the valid edge of the TI010 pin as a trigger, use the output of the TO01 pin that functions alternately as P32. When using the output of the TO01 pin that functions alternately as P35, the TI010 pin that functions alternately as P35 cannot be used.
Page 357 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (2) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because the count of the TM0n register is started asynchronously to the count pulse. Figure 8-46.
Page 358 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (4) Data hold timing of capture register (a) If the valid edge of the TI0n1/TI0n0 pin is input while the CR0n0/CR0n1 register is read, the CR0n0/CR0n1 register performs capture operation, but the read value at this time is not guaranteed. However, the interrupt request signal (INTTM0n0/INTTM0n1) is generated as a result of detection of the valid edge.
Page 359 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (7) Operation of OVF0n flag (a) Setting of OVF0n flag The TMC0n.OVF0n flag is set to 1 in the following case in addition to when the TM0n register overflows. Select the mode in which clear & start occurs upon match between the TM0n register and the CR0n0 register.
Page 360 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (8) One-shot pulse output One-shot pulse output operates normally in either the free-running timer mode or the mode in which clear & start occurs on the valid edge of the TI0n0 pin. In the mode in which clear & start occurs upon match between the TM0n register and the CR0n0 register, one-shot pulse output is not possible.
Page 361 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (10) Edge detection (a) Specifying valid edge after reset If the operation of the 16-bit timer/event counter 0n is enabled after reset and while the TI0n0 or TI0n1 pin is at high level and when the rising edge or both the edges are specified as the valid edge of the TI0n0 or TI0n1 pin, then the high level of the TI0n0 or TI0n1 pin is detected as the rising edge.
Page 362: Chapter 9 8-Bit Timer/Event Counter 5
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 In the V850ES/KG2, two channels of 8-bit timer/event counter 5 are provided. 9.1 Functions 8-bit timer/event counter 5n has the following two modes (n = 0, 1). • Mode using 8-bit timer/event counter alone (individual mode) •...
Page 363: Configuration
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 Figure 9-1. Block Diagram of 8-Bit Timer/Event Counter 5n Internal bus 8-bit timer compare Selector INTTM5n register 5n (CR5n) Match <R> CSI0 serial clock 8-bit timer TI5n TO5n counter 5n Note Count clock (TM5n) Clear Invert level...
Page 364 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 (1) 8-bit timer counter 5n (TM5n) The TM5n register is an 8-bit read-only register that counts the count pulses. The counter is incremented in synchronization with the rising edge of the count clock. Through cascade connection, the TM5n registers can be used as a 16-bit timer. When using the TM50 register and the TM51 register in cascade as a 16-bit timer, these registers can be read only in 16-bit units.
Page 365 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 (2) 8-bit timer compare register 5n (CR5n) The CR5n register can be read and written in 8-bit units. In a mode other than the PWM mode, the value set to the CR5n register is always compared to the count value of the TM5n register, and if the two values match, an interrupt request signal (INTTM5n) is generated.
Page 366: Registers
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.3 Registers The following two registers are used to control 8-bit timer/event counter 5n. • Timer clock selection register 5n (TCL5n) • 8-bit timer mode control register 5n (TMC5n) Remark To use the functions of the TI5n and TO5n pins, refer to Table 4-16 Settings When Port Pins Are Used for Alternate Functions.
Page 367 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 (2) 8-bit timer mode control register 5n (TMC5n) The TMC5n register performs the following six settings. • Controls counting by the TM5n register • Selects the operation mode of the TM5n register • Selects the individual mode or cascade connection mode •...
Page 368 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 After reset: 00H Address: TMC50 FFFFF5C6H, TMC51 FFFFF5C7H <7> <3> <2> <0> Note TMC5n TCE5n TMC5n6 TMC514 LVS5n LVR5n TMC5n1 TOE5n (n = 0, 1) TCE5n Control of count operation of 8-bit timer/event counter 5n Counting is disabled after the counter is cleared to 0 (counter disabled) Start count operation TMC5n6...
Page 369: Operation
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4 Operation 9.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that repeatedly generates interrupts at the interval of the count value preset in the CR5n register. If the count value in the TM5n register matches the value set in the CR5n register, the value of the TM5n register is cleared to 00H and counting is continued, and at the same time, an interrupt request signal (INTTM5n) is generated.
Page 370 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 Figure 9-2. Timing of Interval Timer Operation (2/2) When CR5n register = 00H Count clock TM5n count value CR5n TCE5n INTTM5n Interval time Remark n = 0, 1 When CR5n register = FFH Count clock TM5n count value FEH FFH FEH FFH...
Page 371: Operation As External Event Counter
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4.2 Operation as external event counter The external event counter counts the number of clock pulses input to the TI5n pin from an external source by using the TM5n register. Each time the valid edge specified by the TCL5n register is input to the TI5n pin, the TM5n register is incremented. Either the rising edge or the falling edge can be specified as the valid edge.
Page 372: Square-Wave Output Operation
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4.3 Square-wave output operation A square wave with any frequency can be output at an interval determined by the value preset in the CR5n register. By setting the TMC5n.TOE5n bit to 1, the output status of the TO5n pin is inverted at an interval determined by the count value preset in the CR5n register.
Page 373 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 Figure 9-4. Timing of Square-Wave Output Operation Count clock TM5n count value Count start Clear Clear CR5n TCE5n INTTM5n Interrupt Interrupt acknowledgment acknowledgment Note TO5n Interval time Interval time Note The initial value of the TO5n pin output can be set using the TMC5n.LVS5n and TMC5n.LVR5n bits.
Page 374: 8-Bit Pwm Output Operation
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4.4 8-bit PWM output operation By setting the TMC5n.TMC5n6 bit to 1, 8-bit timer/event counter 5n performs PWM output. Pulses with a duty factor determined by the value set in the CR5n register are output from the TO5n pin. Set the width of the active level of the PWM pulse in the CR5n register.
Page 375 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 (a) Basic operation of PWM output Figure 9-5. Timing of PWM Output Operation Basic operation (active level = H) Count clock TM5n count value N + 1 CR5n TCE5n INTTM5n TO5n Active level Inactive level Active level When CR5n register = 00H Count clock...
Page 376 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 (b) Operation based on CR5n register transitions Figure 9-6. Timing of Operation Based on CR5n Register Transitions When the value of the CR5n register changes from N to M before the rising edge of the FFH clock →...
Page 377: Operation As Interval Timer (16 Bits)
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4.5 Operation as interval timer (16 bits) The 16-bit resolution timer/event counter mode is selected by setting the TMC51.TMC514 bit to 1. 8-bit timer/event counter 5n operates as an interval timer by repeatedly generating interrupts using the count value preset in 16-bit timer compare register 5 (CR5) as the interval.
Page 378 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 Figure 9-7 shows a timing example of the cascade connection mode with 16-bit resolution. Figure 9-7. Cascade Connection Mode with 16-Bit Resolution Count clock N + 1 TM50 count value M − 1 TM51 count value CR50 CR51 TCE50...
Page 379: Operation As External Event Counter (16 Bits)
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4.6 Operation as external event counter (16 bits) The 16-bit resolution timer/event counter mode is selected by setting the TMC51.TMC514 bit to 1. The external event counter counts the number of clock pulses input to the TI50 pin from an external source using 16-bit timer counter 5 (TM5).
Page 380: Square-Wave Output Operation (16-Bit Resolution)
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4.7 Square-wave output operation (16-bit resolution) The 16-bit resolution timer/event counter mode is selected by setting the TMC51.TMC514 bit to 1. 8-bit timer/event counter 5n outputs a square wave of any frequency using the interval preset in 16-bit timer compare register 5 (CR5).
Page 381: Cautions
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4.8 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because the TM5n register is started asynchronously to the count pulse. Figure 9-8.
Page 382: Chapter 10 8-Bit Timer H
CHAPTER 10 8-BIT TIMER H In the V850ES/KG2, two channels of 8-bit timer H are provided. 10.1 Functions 8-bit timer Hn has the following functions (n = 0, 1). • Interval timer • Square ware output • PWM output • Carrier generator 10.2 Configuration...
Page 383 CHAPTER 10 8-BIT TIMER H The block diagram is shown below. Figure 10-1. Block Diagram of 8-Bit Timer Hn Internal bus 8-bit timer H mode 8-bit timer H carrier control register n (TMHMDn) register n (TMCYCn) 8-bit timer H compare 8-bit timer H compare RMCn NRZBn NRZn...
Page 384 CHAPTER 10 8-BIT TIMER H (2) 8-bit timer H compare register n1 (CMPn1) This register can be read or written in 8-bit units. This register is used in the PWM output mode and carrier generator mode. In the PWM output mode, this register constantly compares the value set to the CMPn1 register with the count value of 8-bit timer counter Hn and, when the two values match, inverts the output level of the TOHn pin.
Page 385: Registers
CHAPTER 10 8-BIT TIMER H 10.3 Registers The registers that control 8-bit timer Hn are as follows. • 8-bit timer H mode register n (TMHMDn) • 8-bit timer H carrier control register n (TMCYCn) Remarks 1. To use the TOHn pin function, refer to Table 4-16 Settings When Port Pins Are Used for Alternate Functions.
Page 386 CHAPTER 10 8-BIT TIMER H (a) 8-bit timer H mode register 0 (TMHMD0) After reset: 00H Address: FFFFF580H <7> <1> <0> TMHMD0 TMHE0 CKSH02 CKSH01 CKSH00 TMMD01 TMMD00 TOLEV0 TOEN0 TMHE0 8-bit timer H0 operation enable Stop timer count operation (8-bit timer counter H0 = 00H) Enable timer count operation (Counting starts when clock is input) CKSH02 CKSH01...
Page 387 CHAPTER 10 8-BIT TIMER H (b) 8-bit timer H mode register 1 (TMHMD1) After reset: 00H Address: FFFFF590H <7> <1> <0> TMHMD1 TMHE1 CKSH12 CKSH11 CKSH10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 8-bit timer H1 operation enable Stop timer count operation (8-bit timer counter H1 = 00H) Enable timer count operation (Counting starts when clock is input) CKSH12 CKSH11...
Page 388 CHAPTER 10 8-BIT TIMER H (2) 8-bit timer H carrier control register n (TMCYCn) This register controls the 8-bit timer Hn remote control output and carrier pulse output status. TMCYCn register can be read or written in 8-bit or 1-bit units. The NRZn bit is a read-only bit. Reset sets TMCYCn to 00H.
Page 389: Operation
CHAPTER 10 8-BIT TIMER H 10.4 Operation 10.4.1 Operation as interval timer/square wave output When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. The CMPn1 register cannot be used in the interval timer mode.
Page 390 CHAPTER 10 8-BIT TIMER H Figure 10-3. Timing of Interval Timer/Square Wave Output Operation (1/2) Basic operation (operation when 01H ≤ CMPn0 ≤ FEH) Count clock Count start 8-bit timer counter 01H 00H Hn count value Clear Clear CMPn0 TMHEn INTTMHn Interval time TOHn...
Page 391 CHAPTER 10 8-BIT TIMER H Figure 10-3. Timing of Interval Timer/Square Wave Output Operation (2/2) Operation when CMPn0 = FFH Count clock Count start 8-bit timer counter Hn count value Clear Clear CMPn0 TMHEn Interval time INTTMHn TOHn Operation when CMPn0 = 00H Count clock Count start 8-bit timer counter...
Page 392: Pwm Output Mode Operation
CHAPTER 10 8-BIT TIMER H 10.4.2 PWM output mode operation In the PWM output mode, a pulse of any duty and cycle can be output. The CMPn0 register controls the timer output (TOHn) cycle. Rewriting the CMPn0 register during timer operation is prohibited.
Page 393 CHAPTER 10 8-BIT TIMER H <3> After the count operation is enabled, the first compare register to be compared is the CMPn0 register. When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and the TOHn output level is inverted.
Page 394 CHAPTER 10 8-BIT TIMER H Figure 10-5. Operation Timing in PWM Output Mode (1/4) Basic operation Count clock 8-bit timer counter 00H 01H A5H 00H 01H 02H A5H 00H 01H 02H A5H 00H Hn count value CMPn0 CMPn1 TMHEn INTTMHn TOHn (TOLEVn = 0) <3>...
Page 395 CHAPTER 10 8-BIT TIMER H Figure 10-5. Operation Timing in PWM Output Mode (2/4) Operation when CMPn0 register = FFH, CMPn1 register = 00H Count clock 8-bit timer counter 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H Hn count value CMPn0 CMPn1...
Page 396 CHAPTER 10 8-BIT TIMER H Figure 10-5. Operation Timing in PWM Output Mode (3/4) Operation when CMPn0 register = 01H, CMPn1 register = 00H Count clock 8-bit timer counter 01H 00H 01H 00H 00H 01H 00H 01H Hn count value CMPn0 CMPn1 TMHEn...
Page 397 CHAPTER 10 8-BIT TIMER H Figure 10-5. Operation Timing in PWM Output Mode (4/4) Operation by changing CMPn1 register (CMPn1 register = 02H → 03H, CMPn0 register = A5H) Count clock 8-bit timer 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H counter Hn...
Page 398: Carrier Generator Mode Operation
CHAPTER 10 8-BIT TIMER H 10.4.3 Carrier generator mode operation The carrier clock generated by 8-bit timer Hn is output using the cycle set with 8-bit timer/event counter 5n. In the carrier generator mode, 8-bit timer/event counter 5n is used to control the extent to which the carrier pulse of 8-bit timer Hn is output, and the carrier pulse is output from the TOHn output.
Page 399 CHAPTER 10 8-BIT TIMER H To control carrier pulse output during count operation, the TMCYCn.NRZn and TMCYCn.NRZBn bits have a master and slave bit configuration. The NRZn bit is read-only while the NRZBn bit can be read and written. The INTTM5n signal is synchronized with the 8-bit timer Hn clock and output as the INTTM5Hn signal. The INTTM5Hn signal becomes the data transfer signal of the NRZn bit and the value of the NRZBn bit is transferred to the NRZn bit.
Page 400 CHAPTER 10 8-BIT TIMER H Setting <1> Set each register. Figure 10-7. Register Settings in Carrier Generator Mode • 8-bit timer H mode register n (TMHMDn) TMHEn CKSHn2 CKSHn1 CKSHn0 TMMDn1 TMMDn0 TOLEVn TOENn TMHMDn Enables timer output Sets timer output default level Selects carrier generator mode Selects count clock (f Stops count operation...
Page 401 CHAPTER 10 8-BIT TIMER H Designating the set value of the CMPn0 register as (N), the set value of the CMPn1 register as (M), and the count clock frequency as f , the carrier clock output cycle and duty are as follows. Carrier clock output cycle = (N + M + 2)/f Duty = High level width: Carrier clock output width = (M + 1) : (N + M + 2) Cautions 1.
Page 402 CHAPTER 10 8-BIT TIMER H Figure 10-8. Carrier Generator Mode (1/3) Operation when CMPn0 register and CMPn1 register are set to N 8-bit timer Hn count clock 8-bit timer counter N 00H N 00H N 00H N 00H N 00H Hn count value CMPn0 CMPn1...
Page 403 CHAPTER 10 8-BIT TIMER H Figure 10-8. Carrier Generator Mode (2/3) Operation when CMPn0 register and CMPn1 register are set to N 8-bit timer Hn count clock 8-bit timer counter N 00H 01H M 00H N 00H 01H M 00H Hn count value CMPn0 CMPn1...
Page 404 CHAPTER 10 8-BIT TIMER H Figure 10-8. Carrier Generator Mode (3/3) Operation based on the CMPn1 register transitions 8-bit timer Hn count clock 8-bit timer counter 00H 01H 00H 01H Hn count value CMPn0 <3> <3>' CMPn1 M (L) TMHEn INTTMHn <4>...
Page 405: Chapter 11 Interval Timer, Watch Timer
CHAPTER 11 INTERVAL TIMER, WATCH TIMER The V850ES/KG2 includes interval timer BRG and a watch timer. Interval timer BRG can also be used as the source clock of the watch timer. The watch timer can also be used as interval timer WT.
Page 406 CHAPTER 11 INTERVAL TIMER, WATCH TIMER (1) Clock control The clock control controls supply/stop of the operation clock of interval timer BRG. (2) 3-bit prescaler The 3-bit prescaler divides f to generate f /2, f /4, and f (3) Selector The selector selects the count clock (f ) for interval timer BRG from f /2, f...
Page 407: Registers
CHAPTER 11 INTERVAL TIMER, WATCH TIMER 11.1.3 Registers Interval timer BRG includes the following registers. (1) Interval timer BRG mode register (PRSM) PRSM controls the operation of interval timer BRG, selection of count clock, and clock supply to the watch timer.
Page 408 CHAPTER 11 INTERVAL TIMER, WATCH TIMER (2) Interval timer BRG compare register (PRSCM) PRSCM is an 8-bit compare register. This register can be read or written in 8-bit units. Reset sets PRSCM to 00H. After reset: 00H Address: FFFFF8B1H PRSCM PRSCM7 PRSCM6 PRSCM5 PRSCM4 PRSCM3 PRSCM2 PRSCM1 PRSCM0 Caution Do not rewrite the PRSCM register while interval timer BRG is...
Page 409: Operation
CHAPTER 11 INTERVAL TIMER, WATCH TIMER 11.1.4 Operation (1) Operation of interval timer BRG Set the count clock by using the BGCS1 and BGCS0 bits of PRSM and the 8-bit compare value by using the PRSCM register. When the PRSM.BGCE bit is set (1), interval timer BRG starts operating. Each time the count value of the 8-bit counter and the set value in the PRSCM register match, an interrupt <R>...
Page 410: Watch Timer
CHAPTER 11 INTERVAL TIMER, WATCH TIMER 11.2 Watch Timer 11.2.1 Functions The watch timer has the following functions. • Watch timer: An interrupt request signal (INTWT) is generated at time intervals of 0.5 or 0.25 seconds by using the main clock or subclock. •...
Page 411: Registers
CHAPTER 11 INTERVAL TIMER, WATCH TIMER (1) 11-bit prescaler The 11-bit prescaler generates a clock of f to f by dividing f (2) 5-bit counter The 5-bit counter generates the watch timer interrupt request signal (INTWT) at intervals of 2 or 2 by counting f or f...
Page 412 CHAPTER 11 INTERVAL TIMER, WATCH TIMER After reset: 00H Address: FFFFF680H < > < > WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 WTM7 WTM6 WTM5 WTM4 Selection of interval timer interrupt (INTWTI) time μ (488 s: f μ (977 s: f (1.95 ms: f (3.91 ms: f (7.81 ms: f...
Page 413: Operation
CHAPTER 11 INTERVAL TIMER, WATCH TIMER 11.2.4 Operation (1) Operation as watch timer The watch timer generates an interrupt request at fixed time intervals. The watch timer operates using time intervals of 0.25 or 0.5 seconds with the subclock (32.768 kHz). The count operation starts when the WTM.WTM0 and WTM.WTM1 bits are set to 11.
Page 414: Cautions
CHAPTER 11 INTERVAL TIMER, WATCH TIMER Figure 11-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock or f Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T)
Page 415 CHAPTER 11 INTERVAL TIMER, WATCH TIMER (2) When watch timer and interval timer BRG operate simultaneously When using the subclock as the count clock for the watch timer, the interval time of interval timer BRG can be set to any value. Changing the interval time does not affect the watch timer (before changing the interval time, stop operation).
Page 416: Chapter 12 Watchdog Timer Functions
CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.1 Watchdog Timer 1 12.1.1 Functions Watchdog timer 1 has the following operation modes. • Watchdog timer • Interval timer The following functions are realized from the above-listed operation modes. • Generation of non-maskable interrupt request signal (INTWDT1) upon overflow of watchdog timer 1 Note •...
Page 417 CHAPTER 12 WATCHDOG TIMER FUNCTIONS Figure 12-1. Block Diagram of Watchdog Timer 1 Internal bus Watchdog timer clock Watchdog timer mode selection register (WDCS) register 1 (WDTM1) RUN1 WDTM14 WDTM13 WDCS2 WDCS1 WDCS0 Clear Prescaler INTWDTM1 Output INTWDT1 controller WDTRES1 Remark INTWDTM1: Request signal for maskable interrupt through watchdog timer 1 overflow INTWDT1: Request signal for non-maskable interrupt through watchdog timer 1 overflow...
Page 418: Configuration
CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.1.2 Configuration Watchdog timer 1 includes the following hardware. Table 12-1. Configuration of Watchdog Timer 1 Item Configuration Control register Watchdog timer clock selection register (WDCS) Watchdog timer mode register 1 (WDTM1) 12.1.3 Registers The registers that control watchdog timer 1 are as follows. •...
Page 419 CHAPTER 12 WATCHDOG TIMER FUNCTIONS (2) Watchdog timer mode register 1 (WDTM1) This register sets the watchdog timer 1 operation mode and enables/disables count operations. This register is a special register that can be written only in a special sequence (refer to 3.4.7 Special registers).
Page 420: Operation
CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.1.4 Operation (1) Operation as watchdog timer 1 Watchdog timer 1 operation to detect a program loop is selected by setting the WDTM1.WDTM14 bit to 1. The count clock (program loop detection time interval) of watchdog timer 1 can be selected using the WDCS.WDCS0 to WDCS.WDCS2 bits.
Page 421 CHAPTER 12 WATCHDOG TIMER FUNCTIONS (2) Operation as interval timer Watchdog timer 1 can be made to operate as an interval timer that repeatedly generates interrupts using the count value set in advance as the interval, by clearing the WDTM1.WDTM14 bit to 0. When watchdog timer 1 operates as an interval timer, the interrupt mask flag (WDTMK) and priority specification flags (WDTPR0 to WDTPR2) of the WDTIC register are valid and maskable interrupt request signals (INTWDTM1) can be generated.
Page 422: Watchdog Timer 2
CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.2 Watchdog Timer 2 12.2.1 Functions Watchdog timer 2 has the following functions. • Default start watchdog timer Note 1 → Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDTRES2 signal) →...
Page 423: Configuration
CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.2.2 Configuration Watchdog timer 2 includes the following hardware. Table 12-4. Configuration of Watchdog Timer 2 Item Configuration Control register Watchdog timer mode register 2 (WDTM2) Watchdog timer enable register (WDTE) 12.2.3 Registers (1) Watchdog timer mode register 2 (WDTM2) This register sets the overflow time and operation clock of watchdog timer 2.
Page 424: Watchdog Timer Enable Register (Wdte)
CHAPTER 12 WATCHDOG TIMER FUNCTIONS Table 12-5. Watchdog Timer 2 Clock Selection WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Selected Clock = 20 MHz = 16 MHz = 10 MHz 13.1 ms 16.4 ms 26.2 ms 26.2 ms 32.8 ms 52.4 ms 52.4 ms 65.5 ms 104.9 ms...
Page 425: Operation
CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.2.4 Operation Watchdog timer 2 automatically starts in the reset mode following reset release. The WDTM2 register can be written to only once following reset through byte access. To use watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using 8-bit memory manipulation instructions. After this is done, the operation of watchdog timer 2 cannot be stopped.
Page 426: Chapter 13 Real-Time Output Function (Rto)
Because RTO can output signal without jitter, it is suitable for controlling a stepping motor. In the V850ES/KG2, a 6-bit real-time output port channel is provided. The real-time output port can be set in the port mode or real-time output port mode in 1-bit units.
Page 427: Configuration
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.2 Configuration RTO includes the following hardware. Table 13-1. Configuration of RTO Item Configuration Registers Real-time output buffer register 0 (RTBL0, RTBH0) Control registers Real-time output port mode register 0 (RTPM0) Real-time output port control register 0 (RTPC0) (1) Real-time output buffer register 0 (RTBL0, RTBH0) RTBL0 and RTBH0 are 4-bit registers that hold output data in advance.
Page 428: Registers
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) Table 13-2. Operation During Manipulation of RTBL0 and RTBH0 Registers Note Operation Mode Register to Be Read Write Manipulated Higher 4 bits Lower 4 bits Higher 4 bits Lower 4 bits 4 bits × 1 channel, 2 bits × RTBL0 RTBH0 RTBL0...
Page 429 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register 0 (RTPC0) This register sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Table 13-3.
Page 430: Operation
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.4 Operation If the real-time output operation is enabled by setting the RTPC0.RTPOE0 bit to 1, the data of the RTBH0 and RTBL0 registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the RTPC0.EXTR0 and RTPC0.BYTE0 bits).
Page 431: Usage
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.5 Usage (1) Disable real-time output. Clear the RTPC0.RTPOE0 bit to 0. (2) Perform initialization as follows. • Specify the real-time output port mode or port mode in 1-bit units. Set the RTPM0 register. •...
Page 432: Security Function
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.7 Security Function A circuit that sets the pin outputs to high impedance as a security function for when malfunctions of a stepping motor controlled by RTO occur is provided on chip. It forcibly resets the pins allocated to RTP00 to RTP05 via external interrupt INTP0 pin edge detection, placing them in the high-impedance state.
Page 433 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) (1) PLL control register (PLLCTL) The PLLCTL register is an 8-bit register that controls the RTO security function and PLL. This register can be read or written in 8-bit or 1-bit units. Reset sets PLLCTL to 01H. After reset: 01H Address: FFFFF806H <...
Page 434: Chapter 14 A/D Converter
CHAPTER 14 A/D CONVERTER 14.1 Overview The A/D converter converts analog input signals into digital values and has an 8-channel (ANI0 to ANI7) configuration. The A/D converter has the following functions. ○ Operating voltage (AV ): 2.7 to 5.5 V REF0 ○...
Page 435: Configuration
CHAPTER 14 A/D CONVERTER 14.3 Configuration The A/D converter includes the following hardware. Figure 14-1. Block Diagram of A/D Converter REF0 ADCS bit ANI0 ANI1 Sample & hold circuit ANI2 Voltage comparator ANI3 ANI4 ANI5 SAR register ANI6 ANI7 INTAD INTTM010 Controller Edge...
Page 436 CHAPTER 14 A/D CONVERTER (1) ANI0 to ANI7 pins These are analog input pins for the 8 channels of the A/D converter. They are used to input analog signals to be converted into digital signals. Pins other than those selected as analog input by the ADS register can be used as input ports.
Page 437: Registers
CHAPTER 14 A/D CONVERTER (10) A/D converter mode register (ADM) This register sets the conversion time of the analog input to be converted to a digital signal and the conversion operation start/stop. (11) Analog input channel specification register (ADS) This register specifies the input port for the analog voltage to be converted to a digital signal. (12) Power fail comparison mode register (PFM) This register sets the power fail detection mode.
Page 438 CHAPTER 14 A/D CONVERTER After reset: 00H Address: FFFFF200H < > < > Note 1 Note 1 Note 1 Note 1 Note 1 ADCS ADMD ADHS1 ADHS0 ADCS2 ADCS Control of A/D conversion operation Conversion operation stopped Conversion operation enabled ADMD Control of operation mode Select mode...
Page 439 CHAPTER 14 A/D CONVERTER Table 14-2. A/D Conversion Time μ ADHS1 ADHS0 FR2 A/D Conversion Time ( Conversion Time Mode 20 MHz@ 16 MHz@ 8 MHz@ 8 MHz@ ≥ 4.5 V ≥ 4.0 V ≥ 2.85 V ≥ 2.7 V REF0 REF0 REF0...
Page 440 CHAPTER 14 A/D CONVERTER (a) Controlling reference voltage generator for boosting μ When the ADCS2 bit = 0, power to the A/D converter drops. The converter requires a setup time of 1 μ (high-speed mode) or 14 s (normal mode) or more after the ADCS2 bit has been set to 1. Therefore, the result of A/D conversion becomes valid from the first result by setting the ADCS bit to 1 at μ...
Page 441 CHAPTER 14 A/D CONVERTER (2) Analog input channel specification register (ADS) This register specifies the analog voltage input port for A/D conversion. The ADS register can be read or written in 8-bit or 1-bit units. Reset sets ADS to 00H. After reset: 00H Address: FFFFF201H Note 1...
Page 442 CHAPTER 14 A/D CONVERTER (3) A/D conversion result register, A/D conversion result register H (ADCR, ADCRH) The ADCR and ADCRH registers store the A/D conversion results. These registers are read-only in 16-bit or 8-bit units. However, specify the ADCR register for 16-bit access, and the ADCRH register for 8-bit access.
Page 443 CHAPTER 14 A/D CONVERTER The following shows the relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and A/D conversion results (ADCR register). × 1024 + 0.5) SAR = INT ( REF0 = SAR × 64 Note ADCR REF0...
Page 444 CHAPTER 14 A/D CONVERTER (4) Power fail comparison mode register (PFM) This register sets the power fail detection mode. The PFM register compares the value in the PFT register with the value of the ADCRH register. The PFM register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 445: Operation
CHAPTER 14 A/D CONVERTER 14.5 Operation 14.5.1 Basic operation <1> Select the channel whose analog signal is to be converted into a digital signal using the ADS register. Set the ADM.ADHS1 or ADM.ADHS0 bit. μ μ <2> Set the ADM.ADCS2 bit to 1 and wait 1 s (high-speed mode) or 14 s (normal mode) or longer.
Page 446: Trigger Modes
CHAPTER 14 A/D CONVERTER 14.5.2 Trigger modes The V850ES/KG2 has the following three trigger modes that set the A/D conversion start timing. These trigger modes are set by the ADS register. • Software trigger mode • External trigger mode (hardware trigger mode) •...
Page 447: Operation Modes
CHAPTER 14 A/D CONVERTER 14.5.3 Operation modes The following two operation modes are available. These operation modes are set by the ADM register. • Select mode • Scan mode (1) Select mode One input analog signal specified by the ADS register while the ADM.ADMD bit = 0 is converted. When conversion is complete, the result of conversion is stored in the ADCR register.
Page 448 CHAPTER 14 A/D CONVERTER (2) Scan mode In this mode, the analog signals specified by the ADS register and input from the ANI0 pin while the ADM.ADMD bit = 1 are sequentially selected and converted. When conversion of one analog input signal is complete, the conversion result is stored in the ADCR register and, at the same time, the A/D conversion end interrupt request signal (INTAD) is generated.
Page 449 CHAPTER 14 A/D CONVERTER Figure 14-5. Example of Scan Mode Operation Timing (ADS.ADS2 to ADS.ADS0 Bits = 011B) (a) Timing example ANI0 Data 1 ANI1 Data 2 Data 3 ANI2 Data 4 ANI3 Data 1 Data 2 Data 3 Data 4 A/D conversion (ANI0) (ANI1)
Page 450: Power Fail Detection Function
CHAPTER 14 A/D CONVERTER 14.5.4 Power fail detection function The conversion end interrupt request signal (INTAD) can be controlled as follows using the PFM and PFT registers. • If the PFM.PFEN bit = 0, the INTAD signal is generated each time conversion ends. •...
Page 451: Setting Method
CHAPTER 14 A/D CONVERTER 14.5.5 Setting method The following describes how to set registers. (1) When using the A/D converter for A/D conversion <1> Set (1) the ADM.ADCS2 bit. <2> Select the channel and conversion time by setting the ADS.ADS2 to ADS.ADS0 bits and the ADM.ADHS1, ADM.ADHS0, and ADM.FR2 to ADM.FR0 bits.
Page 452: Cautions
CHAPTER 14 A/D CONVERTER 14.6 Cautions (1) Power consumption in standby mode The operation of the A/D converter stops in the standby mode. At this time, the power consumption can be reduced by stopping the conversion operation (the ADM.ADCS bit = 0) and the reference voltage generator (the ADM.ADCS2 bit = 0).
Page 453 CHAPTER 14 A/D CONVERTER (4) Measures against noise To keep a resolution of 10 bits, be aware of noise on the AV and ANI0 to ANI7 pins. The higher the output REF0 impedance of the analog input source, the greater the effect of noise. Therefore, it is recommended to connect external capacitors as shown in Figure 14-8 to reduce noise.
Page 454 CHAPTER 14 A/D CONVERTER (7) Interrupt request flag (ADIC.ADIF bit) Even when the ADS register is changed, the ADIF bit is not cleared (0). Therefore, if the analog input pin is changed during A/D conversion, the ADIF bit may be set (1) because A/D conversion of the previous analog input pin ends immediately before the ADS register is rewritten.
Page 455 CHAPTER 14 A/D CONVERTER (10) A/D converter sampling time and A/D conversion start delay time The A/D converter sampling time differs depending on the set value of the ADM register. A delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required for the contents shown in Figure 14-10 and Table 14-4.
Page 456 CHAPTER 14 A/D CONVERTER Table 14-4. A/D Converter Conversion Time ADHS1 ADHS0 Conversion Time Sampling Time Register Write Trigger Response Note Note Response Time Time MIN. MAX. MIN. MAX. 288/f 176/f 11/f 12/f 240/f 176/f 11/f 12/f 192/f 132/f 10/f 11/f 144/f 88/f...
Page 457 CHAPTER 14 A/D CONVERTER (11) Internal equivalent circuit The following shows the equivalent circuit of the analog input block. Figure 14-11. Internal Equivalent Circuit of ANIn Pin ANIn REF0 4.5 V 3 kΩ 8 pF 15 pF 2.7 V 60 kΩ 8 pF 15 pF Remarks 1.
Page 458: How To Read A/D Converter Characteristics Table
CHAPTER 14 A/D CONVERTER 14.7 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1 LSB (Least Significant Bit).
Page 459 CHAPTER 14 A/D CONVERTER (3) Quantization error When analog values are converted to digital values, a ±1/2 LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of ±1/2 LSB is converted to the same digital code, so a quantization error cannot be avoided.
Page 460 CHAPTER 14 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (full scale − 3/2 LSB) when the digital output changes from 1……110 to 1……111. Figure 14-15. Full-Scale Error Full-scale error –3 –2...
Page 461 CHAPTER 14 A/D CONVERTER (7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0.
Page 462: Chapter 15 D/A Converter
CHAPTER 15 D/A CONVERTER 15.1 Functions In the V850ES/KG2, two channels of D/A converter (DAC0, DAC1) are provided. The D/A converter has the following functions. 8-bit resolution × 2 channels R-2R ladder string method μ Conversion time: 20 s (MAX.) (AV = 2.7 to 5.5 V)
Page 463: Configuration
CHAPTER 15 D/A CONVERTER 15.2 Configuration The D/A converter configuration is shown below. Figure 15-1. Block Diagram of D/A Converter DACS0 register write DACS0 DAM.DAMD0 bit INTTMH0 signal ANO0 DACE0 Selector REF1 ANO1 Selector DACE1 DACS1 register write DAM.DAMD1 bit DACS1 INTTMH1 signal Caution DAC0 and DAC1 share the AV...
Page 464: Registers
CHAPTER 15 D/A CONVERTER 15.3 Registers The registers that control the D/A converter are as follows. • D/A converter mode register (DAM) • D/A conversion value setting registers 0 and 1 (DACS0, DACS1) (1) D/A converter mode register (DAM) This register controls the operation of the D/A converter. The DAM register can be read or written in 8-bit or 1-bit units.
Page 465: Operation
CHAPTER 15 D/A CONVERTER 15.4 Operation 15.4.1 Operation in normal mode D/A conversion is performed using a write operation to the DACSn register as the trigger. The setting method is described below. <1> Clear the DAM.DAMDn bit to 0 (normal mode). <2>...
Page 466: Cautions
CHAPTER 15 D/A CONVERTER 15.4.3 Cautions Observe the following cautions when using the D/A converter. • When using the D/A converter, set the port pins to the input mode (PM10, PM11 bits = 11) • When using the D/A converter, reading of the port is prohibited. •...
Page 467: Chapter 16 Asynchronous Serial Interface (Uart)
16.1 Selecting UART2 or CSI00 Mode UART2 and CSI00 of the V850ES/KG2 share pins, and therefore these interfaces cannot be used at the same time. Select UART2 or CSI00 in advance by using the PMC4 and PFC4 registers (refer to 4.3.4 Port 4).
Page 468: Features
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.2 Features • Maximum transfer speed: 312.5 kbps • Full-duplex communications On-chip RXBn register On-chip TXBn register • Two-pin configuration Note TXDn: Transmit data output pin RXDn: Receive data input pin • Reception error detection functions •...
Page 469: Configuration
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.3 Configuration Table 16-1. Configuration of UARTn Item Configuration Registers Receive buffer register n (RXBn) Transmit buffer register n (TXBn) Receive shift register Transmit shift register Asynchronous serial interface mode register n (ASIMM) Asynchronous serial interface status register n (ASISn) Asynchronous serial interface transmit status register n (ASIFn) Other Reception control parity check...
Page 470 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (7) Transmit shift register This is a shift register that converts the parallel data that was transferred from the TXBn register to serial data. When one byte of data is transferred from the TXBn register, the shift register data is output from the TXDn pin.
Page 471: Registers
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.4 Registers (1) Asynchronous serial interface mode register n (ASIMn) The ASIMn register is an 8-bit register that controls the UARTn transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 01H.
Page 472 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (2/2) RXEn Reception enable/disable Note Disable reception Enable reception • Set the RXEn bit to 1 after setting the UARTEn bit to 1 at startup. Clear the UARTEn bit to 0 after clearing the RXEn bit to 0 to stop.
Page 473 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (2) Asynchronous serial interface status register n (ASISn) The ASISn register, which consists of 3 error flag bits (PEn, FEn and OVEn), indicates the error status when UARTn reception is complete. The ASISn register is cleared to 00H by a read operation. When a reception error occurs, the RXBn register should be read and the error flag should be cleared after the ASISn register is read.
Page 474 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (3) Asynchronous serial interface transmit status register n (ASIFn) The ASIFn register, which consists of 2 status flag bits, indicates the status during transmission. By writing the next data to the TXBn register after data is transferred from the TXBn register to the transmit shift register, transmit operations can be performed continuously without suspension even during an interrupt interval.
Page 475 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (4) Receive buffer register n (RXBn) The RXBn register is an 8-bit buffer register for storing parallel data that had been converted by the receive shift register. When reception is enabled (ASIMn.RXEn bit = 1), receive data is transferred from the receive shift register to the RXBn register, synchronized with the completion of the shift-in processing of one frame.
Page 476 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (5) Transmit buffer register n (TXBn) The TXBn register is an 8-bit buffer register for setting transmit data. When transmission is enabled (ASIMn.TXEn bit = 1), the transmit operation is started by writing data to TXBn register.
Page 477: Interrupt Requests
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.5 Interrupt Requests The following three types of interrupt request signals are generated from UARTn. • Reception error interrupt request signal (INTSREn) • Reception completion interrupt request signal (INTSRn) • Transmission completion interrupt request signal (INTSTn) The default priorities among these three types of interrupt request signals are, from high to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt.
Page 478: Operation
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.6 Operation 16.6.1 Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 16-3. The character bit length within one data frame, the type of parity, and the stop bit length are specified according to the ASIMn register.
Page 479: Transmit Operation
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.6.2 Transmit operation When the ASIMn.UARTEn bit is set to 1, a high level is output from the TXDn pin. Then, when the ASIMn.TXEn bit is set to 1, transmission is enabled, and the transmit operation is started by writing transmit data to the TXBn register.
Page 480 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) Figure 16-4. UARTn Transmission Completion Interrupt Timing (a) Stop bit length: 1 Start TXDn (output) Parity Stop INTSTn (output) (b) Stop bit length: 2 Stop Parity TXDn (output) Start INTSTn (output) User’s Manual U17703EJ2V0UD...
Page 481: Continuous Transmission Operation
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.6.3 Continuous transmission operation UARTn can write the next transmit data to the TXBn register at the timing that the transmit shift register starts the shift operation. This enables an efficient transmission rate to be realized by continuously transmitting data even during the transmission completion interrupt service after the transmission of one data frame.
Page 482 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) Figure 16-5. Continuous Transmission Processing Flow Set registers Write transmit data to TXBn register When reading ASIFn register, TXBFn = 0? Write second byte transmit data to TXBn register Interrupt occurrence Required number of transfers performed? When reading When reading...
Page 483: Starting Procedure
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (1) Starting procedure The procedure to start continuous transmission is shown below. Figure 16-6. Continuous Transmission Starting Procedure Start Start Stop Stop TXDn (output) Data (1) Data (2) <1> <2> <3> <4> <5> INTSTn (output) TXBn register Data (1) Data (2)
Page 484: Ending Procedure
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (2) Ending procedure The procedure for ending continuous transmission is shown below. Figure 16-7. Continuous Transmission End Procedure Start Start Stop Stop TXDn (output) Data (m − 1) Data (m) <6> <7> <8> <9> <10>...
Page 485: Receive Operation
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.6.4 Receive operation The awaiting reception state is set by setting the ASIMn.UARTEn bit to 1 and then setting the ASIMn.RXEn bit to 1. To start the receive operation, start sampling at the falling edge when the falling of the RXDn pin is detected. If the RXDn pin is low level at a start bit sampling point, the start bit is recognized.
Page 486: Reception Error
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) Figure 16-8. UARTn Reception Completion Interrupt Timing RXDn (input) Start Parity Stop INTSRn (output) RXBn register Cautions 1. Be sure to read the RXBn register even when a reception error occurs. If the RXBn register is not read, an overrun error will occur at the next data reception and the reception error status will continue infinitely.
Page 487 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (1) Separation of reception error interrupt request signal A reception error interrupt request signal can be separated from the INTSRn signal and generated as the INTSREn signal by clearing the ISRMn bit to 0. Figure 16-9.
Page 488: Parity Types And Corresponding Operation
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.6.6 Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used on the transmission and reception sides. (1) Even parity (i) During transmission The parity bit is controlled so that the number of bits with the value “1”...
Page 489: Receive Data Noise Filter
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.6.7 Receive data noise filter The RXDn signal is sampled at the rising edge of the prescaler output base clock (f ). If the same sampling UCLK value is obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (refer to Figure 16-12).
Page 490: Dedicated Baud Rate Generator N (Brgn)
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.7 Dedicated Baud Rate Generator n (BRGn) A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by UARTn. The dedicated baud rate generator output can be selected as the serial clock for each channel.
Page 491: Serial Clock Generation
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.7.2 Serial clock generation A serial clock can be generated according to the settings of the CKSRn and BRGCn registers. The base clock to the 8-bit counter is selected by the CKSRn.TPSn3 to CKSRn.TPSn0 bits. The 8-bit counter divisor value can be set by the BRGCn.MDLn7 to BRGCn.MDLn0 bits.
Page 492 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (2) Baud rate generator control register n (BRGCn) The BRGCn register is an 8-bit register that controls the baud rate (serial transfer speed) of UARTn. This register can be read or written in 8-bit units. Reset sets this register to FFH.
Page 493 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (3) Baud rate The baud rate is the value obtained by the following formula. UCLK Baud rate [bps] = 2 × k = Frequency [Hz] of base clock selected by CKSRn.TPSn3 to CKSRn.TPSn0 bits. UCLK k = Value set by BRGCn.MDLn7 to BRGCn.MDLn0 bits (k = 8, 9, 10, ..., 255) (4) Baud rate error...
Page 494: Baud Rate Setting Example
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.7.3 Baud rate setting example Table 16-4. Baud Rate Generator Setting Data = 20 MHz = 16 MHz = 10 MHz Baud Rate (bps) UCLK UCLK UCLK /512 41H (65) 0.16 /1024 1AH (26) 0.16 /256 41H (65)
Page 495: Allowable Baud Rate Range During Reception
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.7.4 Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range.
Page 496 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) Therefore, the transfer destination’s maximum receivable baud rate (BRmax) is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows. − × ×...
Page 497: Transfer Rate During Continuous Transmission
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.7.5 Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit.
Page 498: Chapter 17 Clocked Serial Interface 0 (Csi0)
CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) In the V850ES/KG2, two channels of clocked serial interface 0 (CSI0) are provided. 17.1 Features • Maximum transfer speed: 5 Mbps • Master mode/slave mode selectable • Transmission data length: 8 bits or 16 bits can be set •...
Page 499: Configuration
CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) 17.2 Configuration CSI0n is controlled via the CSIM0n register. (1) Clocked serial interface mode register 0n (CSIM0n) The CSIM0n register is an 8-bit register that specifies the operation of CSI0n. (2) Clocked serial interface clock selection register n (CSICn) The CSICn register is an 8-bit register that controls the CSI0n serial transfer operation.
Page 500 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (12) Clocked serial interface initial transmit buffer register nL (SOTBFnL) The SOTBFnL register is an 8-bit buffer register that stores initial transmit data in the continuous transfer mode. (13) Selector The selector selects the serial clock to be used. (14) Serial clock controller Controls the serial clock supply to the shift register.
Page 501 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 17-1. Block Diagram of Clocked Serial Interface Serial clock controller SCK0n Clock start/stop control Selector & clock phase control Interrupt INTCSI0n controller TO50, TO51 SCK0n Transmission control Transmission data control Control signal Initial transmit SO selection SO0n...
Page 502: Registers
CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) 17.3 Registers (1) Clocked serial interface mode register 0n (CSIM0n) The CSIM0n register controls the CSI0n operation. This register can be read or written in 8-bit or 1-bit units (however, CSOTn bit is read-only). Reset sets CSIM0n to 00H.
Page 503 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) After reset: 00H Address: CSIM00 FFFFFD00H, CSIM01 FFFFFD10H <7> <6> <4> <0> CSIM0n CSI0En TRMDn CCLn DIRn CSITn AUTOn CSOTn (n = 0, 1) CSI0En CSI0n operation enable/disable Disable CSI0n operation. Enable CSI0n operation. Note The internal CSI0n circuit can be reset asynchronously by clearing the CSI0En bit to 0.
Page 504 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (2) Clocked serial interface clock selection register n (CSICn) The CSICn register is an 8-bit register that controls the CSI0n transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets CSICn to 00H.
Page 505 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (3) Clocked serial interface receive buffer registers n, nL (SIRBn, SIRBnL) The SIRBn register is a 16-bit buffer register that stores receive data. When the receive-only mode is set (CSIM0n.TRMDn bit = 0), the reception operation is started by reading data from the SIRBn register.
Page 506 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (4) Clocked serial interface read-only receive buffer registers n, nL (SIRBEn, SIRBEnL) The SIRBEn register is a 16-bit buffer register that stores receive data. The SIRBEn register is the same as the SIRBn register. Even if the SIRBEn register is read, the next operation will not start.
Page 507 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (5) Clocked serial interface transmit buffer registers n, nL (SOTBn, SOTBnL) The SOTBn register is a 16-bit buffer register that stores transmit data. When the transmission/reception mode is set (CSIM0n.TRMDn bit = 1), the transmission operation is started by writing data to the SOTBn register.
Page 508 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (6) Clocked serial interface initial transmit buffer registers n, nL (SOTBFn, SOTBFnL) The SOTBFn register is a 16-bit buffer register that stores initial transmission data in the continuous transfer mode. The transmission operation is not started even if data is written to the SOTBFn register. This register can be read or written in 16-bit units.
Page 509 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Serial I/O shift registers n, nL (SIO0n, SIO0nL) The SIO0n register is a 16-bit shift register that converts parallel data into serial data. The transfer operation is not started even if the SIO0n register is read. This register is read-only in 16-bit units.
Page 510 Table 17-1. Use of Each Buffer Register Note 1 Register Single Transfer Continuous Transfer Name Transmission/Reception Mode Receive-Only Mode Transmission/Reception Mode Receive-Only Mode • Reading starts reception Storing up to the (N − 1)th received data • Reading starts reception Note 2 SIRBn Read...
Page 511: Operation
CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) 17.4 Operation 17.4.1 Transmission/reception completion interrupt request signal (INTCSI0n) The INTCSI0n signal is set (1) upon completion of data transmission/reception. Writing to the CSIM0n register clears (0) the INTCSI0n signal. Caution The delay mode (CSIM0n.CSITn bit = 1) is valid only in the master mode (CSICn.CKS0n2 to CSICn.CKS0n0 bits are not 111B).
Page 512 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 17-2. Timing Chart of INTCSI0n Signal Output in Delay Mode (a) Transmit/receive type 1 Input clock SCK0n (I/O) SI0n (input) SO0n (output) Reg_R/W INTCSI0n signal CSOTn bit Delay (b) Transmit/receive type 4 Input clock SCK0n (I/O) SI0n (input)
Page 513: Single Transfer Mode
CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) 17.4.2 Single transfer mode (1) Usage In the receive-only mode (CSIM0n.TRMDn bit = 0), communication is started by reading the SIRBn/SIRBnL register. In the transmission/reception mode (TRMDn bit = 1), communication is started by writing to the SOTBn/SOTBnL register.
Page 514 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 17-3. Timing Chart in Single Transfer Mode (1/2) (a) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, when AAH is received and 55H is transmitted, transmit/receive type 1 SCK0n (I/O) (55H) SO0n (output)
Page 515 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 17-3. Timing Chart in Single Transfer Mode (2/2) (b) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, when AAH is received and 55H is transmitted, transmit/receive type 2 SCK0n (I/O) SO0n (output) (55H)
Page 516: Continuous Transfer Mode
CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) 17.4.3 Continuous transfer mode (1) Usage (receive-only: 8-bit data length) <1> Set the continuous transfer mode (CSIM0n.AUTOn bit = 1) and the receive-only mode (CSIM0n.TRMDn bit = 0). <2> Read the SIRBnL register (start transfer with dummy read). <3>...
Page 517 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 17-4. Continuous Transfer (Receive-Only) Timing Chart • Transmit/receive type 1, 8-bit data length SCK0n (I/O) din-1 din-2 din-3 din-4 din-5 SI0n (input) SIO0nL din-5 register SIRBnL din-1 din-2 din-3 din-4 register SIRBEn (d4) Reg-RD SIRBn (1) SIRBn (d2)
Page 518 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (2) Usage (transmission/reception: 8-bit data length) <1> Set the continuous transfer mode (CSIM0n.AUTOn bit = 1) and the transmission/reception mode (CSIM0n.TRMDn bit = 1). <2> Write the first data to the SOTBFnL register. <3>...
Page 519 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 17-5. Continuous Transfer (Transmission/Reception) Timing Chart • Transmit/receive type 1, 8-bit data length SCK0n (I/O) SO0n (output) dout-1 dout-2 dout-3 dout-4 dout-5 SI0n (input) din-1 din-2 din-3 din-4 din-5 SOTBFnL dout-1 register SOTBnL dout-2 dout-3...
Page 520 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (3) Next transfer reservation period In the continuous transfer mode, the next transfer must be prepared with the period shown in Figure 17-6. Figure 17-6. Timing Chart of Next Transfer Reservation Period (1/2) (a) When data length: 8 bits, transmit/receive type 1 SCK0n (I/O)
Page 521 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 17-6. Timing Chart of Next Transfer Reservation Period (2/2) (c) When data length: 8 bits, transmit/receive type 2 SCK0n (I/O) INTCSI0n signal Reservation period: 6.5 SCK0n cycles (d) When data length: 16 bits, transmit/receive type 2 SCK0n (I/O) INTCSI0n...
Page 522 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (4) Cautions To continue continuous transfers, it is necessary to either read the SIRBn register or write to the SOTBn register during the transfer reservation period. If access is performed to the SIRBn register or the SOTBn register when the transfer reservation period is over, the following occurs.
Page 523 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (ii) In case of conflict between transmission/reception completion interrupt request signal (INTCSI0n) generation and register access Since continuous transfer has stopped once, executed as a new continuous transfer. In the slave mode, a bit phase error transfer error results (refer to Figure 17-8). In the transmission/reception mode, the value of the SOTBFn register is retransmitted, and illegal data is sent.
Page 524: Output Pins
CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) 17.5 Output Pins The following describes the output pins. For the setting of each pin, refer to Table 4-16 Settings When Port Pins Are Used for Alternate Functions. (1) SCK0n pin When the CSI0n operation is disabled (CSIM0n.CSI0En bit = 0), the SCK0n pin output status is as follows. Table 17-2.
Page 525: Chapter 18 Clocked Serial Interface A (Csia) With Automatic Transmit/Receive Function
CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION In the V850ES/KG2, two channels of clocked serial interface A (CSIA) with automatic transmit/receive function are provided. 18.1 Functions CSIAn has the following two modes. • 3-wire serial I/O mode •...
Page 526: Configuration
CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION 18.2 Configuration CSIAn includes the following hardware. Table 18-1. Configuration of CSIAn Item Configuration Register Serial I/O shift register An (SIOAn) Automatic data transfer address count register n (ADTCn) CSIAn buffer RAM (CSIAnBm, CSIAnBmL, CSIAnBmH) (m = 0 to F) Control registers Serial operation mode specification register n (CSIMAn)
Page 527 Figure 18-1. Block Diagram of CSIAn Automatic data Automatic data transfer address transfer address Buffer RAM point specification count register n register n (ADTPn) (ADTCn) Internal bus Serial trigger register n (CSITn) DIRAn ATMn Divisor selection Serial I/O shift register n ATSTPn ATSTAn SIAn register An (SIOAn)
Page 528: Registers
CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (1) Serial I/O shift register An (SIOAn) This is an 8-bit register used to store transmit/receive data in 1-byte transfer mode (CSIMAn.ATEn bit = 0). Writing transmit data to the SIOAn register starts the transfer. In addition, after a transfer completion interrupt request signal (INTCSIAn) is generated (CSISn.TSFn bit = 0), data can be received by reading data from the SIOAn register.
Page 529 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (1) Serial operation mode specification register n (CSIMAn) This is an 8-bit register used to control the serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 530 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (2) Serial status register n (CSISn) This is an 8-bit register used to select the serial clock and to indicate the transfer status of CSIAn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 531 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (3) Serial trigger register n (CSITn) The CSITn register between the buffer RAM and shift register is an 8-bit register used to control execution/stop of automatic data transfer. This register can be read or written in 8-bit or 1-bit units. However, manipulate only when the CSIMAn.ATEn bit is 1 (manipulation prohibited when ATEn bit = 0).
Page 532 ADTPn register is prohibited. Reset sets this register to 00H. In the V850ES/KG2, 00H to 1FH can be specified because 32 bytes of buffer RAM are incorporated. Example When the ADTP0 register is set to 07H 8 bytes of FFFFFE00H to FFFFFE07H are transferred.
Page 533 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION The relationship between buffer RAM address values and the ADTPn register setting values is shown below. Table 18-2. Relationship Between Buffer RAM Address Values and ADTP0 Register Setting Values Buffer RAM Address Value ADTP0 Register Setting Value Buffer RAM Address Value...
Page 534 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (6) Automatic data transfer interval specification register n (ADTIn) This is an 8-bit register used to specify the interval period between 1-byte transfers during automatic data transfer (CSIMAn.ATEn bit = 1). Set this register when in master mode (CSIMAn.MASTERn bit = 1) (setting is unnecessary in slave mode).
Page 535 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Table 18-4. CSIA0 Buffer RAM Address Symbol Manipulatable Bits After Reset √ FFFFFE00H CSIA0B0 Undefined √ FFFFFE00H CSIA0B0L Undefined √ FFFFFE01H CSIA0B0H Undefined √ FFFFFE02H CSIA0B1 Undefined √ FFFFFE02H CSIA0B1L Undefined √...
Page 536 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Table 18-5. CSIA1 Buffer RAM Address Symbol Manipulatable Bits After Reset √ FFFFFE20H CSIA1B0 Undefined √ FFFFFE20H CSIA1B0L Undefined √ FFFFFE21H CSIA1B0H Undefined √ FFFFFE22H CSIA1B1 Undefined √ FFFFFE22H CSIA1B1L Undefined √...
Page 537: Operation
CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION 18.4 Operation CSIAn can be used in the following two modes. • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 18.4.1 3-wire serial I/O mode The one-byte data transmission/reception is executed in the mode in which the CSIMAn.ATEn bit is cleared to 0.
Page 538 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (1) 1-byte transmission/reception communication operation (a) 1-byte transmission/reception When the CSIMAn.CSIAEn bit and the CSIMAn.ATEn bit = 1, 0, respectively, if transfer data is written to the SIOAn register, the data is output via the SOA0 pin in synchronization with the SCKAn pin falling edge, and then input via the SIAn pin in synchronization with the falling edge of the SCKAn pin, and stored in the SIOAn register in synchronization with the rising edge 1 clock later.
Page 539 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (b) Data format In the data format, data is changed in synchronization with the SCKAn pin falling edge as shown in Figure 18-3. The data length is fixed to 8 bits and the data transfer direction can be switched by the specification of the CSIMAn.DIRAn bit.
Page 540 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (c) Switching MSB/LSB as start bit Figure 18-4 shows the configuration of the SIOAn register and the internal bus. As shown in the figure, MSB/LSB can be read or written in reverse form. Switching MSB/LSB as the start bit can be specified using the CSIMAn.DIRAn bit.
Page 541: 3-Wire Serial I/O Mode With Automatic Transmit/Receive Function
CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION 18.4.2 3-wire serial I/O mode with automatic transmit/receive function Up to 32 bytes of data can be transmitted/received without using software in the mode in which the CSIMAn.ATEn bit is set to 1. After communication is started, only data of the set number of bytes stored in RAM in advance can be transmitted, and only data of the set number of bytes can be received and stored in RAM.
Page 542 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (2) Automatic transmission/reception communication operation (a) Automatic transmission/reception mode Automatic transmission/reception can be performed using buffer RAM. The data stored in the buffer RAM is output from the SOAn pin via the SIOAn register in synchronization with the SCKAn pin falling edge by performing (a) and (b) in (1) Automatic transmit/receive data setting.
Page 543 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Figure 18-5. Automatic Transmission/Reception Mode Operation Timings Interval Interval SCKAn SOAn D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIAn D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 INTCSIAn TSFn...
Page 544 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Figure 18-6. Automatic Transmission/Reception Mode Flowchart Start Write transmit data in buffer RAM Set ADTPn register to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set automatic transmission/...
Page 545 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION In 6-byte transmission/reception (CSIMAn.ATMn bit = 0, CSIMAn.RXEAn bit = 1, CSIMAn.TXEAn bit = 1) in automatic transmission/reception mode, buffer RAM operates as follows. (i) When transmission/reception operation is started (refer to Figure 18-7 (a).) When the CSITn.ATSTAn bit is set to 1, transmit data 1 (T1) is transferred from the buffer RAM to the SIOAn register.
Page 546 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Figure 18-7. Buffer RAM Operation in 6-Byte Transmission/Reception (in Automatic Transmission/Reception Mode) (2/2) (b) 4th byte transmission/reception FFFFFE1FH FFFFFE05H Transmit data 6 (R6) Receive data 4 (R4) SIOAn register Transmit data 5 (R5) ADTPn register Transmit data 4 (R4)
Page 547 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (b) Automatic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when the CSITn.ATSTAn bit is set to 1 while the CSIMAn.CSIAEn, CSIMAn.ATEn, and CSIMAn.TXEAn bits are set to 1.
Page 548 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Figure 18-9. Automatic Transmission Mode Flowchart Start Write transmit data in buffer RAM Set ADTPn register to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set automatic transmission mode Set CSITn.ATSTAn bit to 1...
Page 549 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION In 6-byte transmission (CSIMAn.ATMn bit = 0, CSIMAn.RXEAn bit = 0, CSIMAn.TXEAn bit = 1, CSIMAn.ATEn bit = 1) in automatic transmission mode, buffer RAM operates as follows. (i) When transmission is started (refer to Figure 18-10 (a).) When the CSITn.ATSTAn bit is set to 1, transmit data 1 (T1) is transferred from the buffer RAM to the SIOAn register.
Page 550 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Figure 18-10. Buffer RAM Operation in 6-Byte Transmission (in Automatic Transmission Mode) (2/2) (b) 4th byte transmission point FFFFFE1FH FFFFFE05H Transmit data 6 (T6) SIOAn register Transmit data 5 (T5) ADTPn register Transmit data 4 (T4) Transmit data 3 (T3)
Page 551 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (c) Repeat transmission mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer is started when the CSITn.ATSTAn bit is set to 1 while the CSIMAn.CSIAEn, CSIMAn.ATEn, CSIMAn.ATMn, and CSIMAn.TXEAn bits are set to 1.
Page 552 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Figure 18-12. Repeat Transmission Mode Flowchart Start Write transmit data in buffer RAM Set ADTPn register to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set repeat transmission mode Set CSITn.ATSTAn bit to 1...
Page 553 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION In 6-byte transmission (CSIMAn.ATMn bit = 1, CSIMAn.RXEAn bit = 0, CSIMAn.TXEAn bit = 1, CSIMAn.ATEn bit = 1) in repeat transmission mode, buffer RAM operates as follows. (i) When transmission is started (refer to Figure 18-13 (a).) When the CSITn.ATSTAn bit is set to 1, transmit data 1 (T1) is transferred from the buffer RAM to the SIOAn register.
Page 554 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Figure 18-13. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) (2/2) (b) Upon completion of transmission of 6 bytes FFFFFE1FH FFFFFE05H Transmit data 6 (T6) SIOAn register Transmit data 5 (T5) ADTPn register Transmit data 4 (T4)
Page 555 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (d) Data format In the data format, data is changed in synchronization with the SCKAn pin falling edge as shown in Figure 18-14. The data length is fixed to 8 bits and the data transfer direction can be switched by the specification of the CSIMAn.DIRAn bit.
Page 556 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (e) Automatic transmission/reception suspension and restart Automatic transmission/reception can be temporarily suspended by setting the CSITn.ATSTPn bit to 1. During 8-bit data transfer, the transmission/reception is not suspended. It is suspended upon completion of 8-bit data transfer.
Page 557: Chapter 19 I 2 C Bus
C bus function, use the P38/SDA0 and P39/SCL0 pins as the serial transmit/receive data I/O pin (SDA0) and serial clock I/O pin (SCL0), respectively, and set them to N-ch open-drain output. In the V850ES/KG2, one channel of I C bus is provided.
Page 558 CHAPTER 19 I C BUS Figure 19-1. Block Diagram of I Internal bus IIC status register 0 (IICS0) MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IIC control register 0 (IICC0) IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 Start Slave address Clear condition...
Page 559 CHAPTER 19 I C BUS A serial bus configuration example is shown below. Figure 19-2. Serial Bus Configuration Example Using I C Bus Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2 Slave CPU3 Address 3 Slave IC...
Page 560: Configuration
CHAPTER 19 I C BUS 19.2 Configuration C0 includes the following hardware. Table 19-1. Configuration of I Item Configuration Registers IIC shift register 0 (IIC0) Slave address register 0 (SVA0) Control registers IIC control register 0 (IICC0) IIC status register 0 (IICS0) IIC flag register 0 (IICCF0) IIC clock selection register 0 (IICCL0) IIC function expansion register 0 (IICX0)
Page 561 CHAPTER 19 I C BUS (8) Serial clock controller In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock. (9) Serial clock wait controller This circuit controls the wait timing. (10) ACK generator, stop condition detector, start condition detector, and ACK detector These circuits are used to generate and detect various statuses.
Page 562: Registers
CHAPTER 19 I C BUS 19.3 Registers C0 is controlled by the following registers. • IIC control register 0 (IICC0) • IIC status register 0 (IICS0) • IIC flag register 0 (IICF0) • IIC clock selection register 0 (IICCL0) • IIC function expansion register 0 (IICX0) The following registers are also used.
Page 563 CHAPTER 19 I C BUS (1/4) After reset: 00H Address: IICC0 FFFFFD82H <7> <6> <5> <4> <3> <2> <1> <0> IICC0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 IICE0 C0 operation enable/disable specification Note 1 Stop operation. Reset the IICS0 register .
Page 564 CHAPTER 19 I C BUS (2/4) Note SPIE0 Enable/disable generation of interrupt request when stop condition is detected Disable Enable Condition for clearing (SPIE0 bit = 0) Condition for setting (SPIE0 bit = 1) • Cleared by instruction • Set by instruction •...
Page 565 CHAPTER 19 I C BUS (3/4) STT0 Start condition trigger Do not generate a start condition. When bus is released (in STOP mode): Generate a start condition (for starting as master). The SDA0 line is changed from high level to low level while the SCL0 line is high level and then the start condition is generated.
Page 566 CHAPTER 19 I C BUS (4/4) SPT0 Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until the SCL0 pin goes to high level.
Page 567 CHAPTER 19 I C BUS (2) IIC status register 0 (IICS0) The IICS0 register indicates the status of the I C0 bus. The IICS0 register is read-only, in 8-bit or 1-bit units. However, the IICS0 register can only be read when the IICC0.STT0 bit is 1 or during the wait period. Reset sets this register to 00H.
Page 568 CHAPTER 19 I C BUS (2/3) EXC0 Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXC0 bit = 0) Condition for setting (EXC0 bit = 1) • When a start condition is detected •...
Page 569 CHAPTER 19 I C BUS (3/3) ACKD0 Detection of ACK ACK was not detected. ACK was detected. Condition for clearing (ACKD0 bit = 0) Condition for setting (ACKD0 bit = 1) • When a stop condition is detected • After the SDA0 pin is set to low level at the rising edge of •...
Page 570 CHAPTER 19 I C BUS (3) IIC flag register 0 (IICF0) IICF0 is a register that set the operation mode of I C0 and indicate the status of the I C bus. These registers can be read or written in 8-bit or 1-bit units. However, the STCF0 and IICBSY0 bits are read- only.
Page 571 CHAPTER 19 I C BUS Note After reset: 00H Address: IICF0 FFFFFD8AH <7> <6> <1> <0> IICF0 STCF0 IICBSY0 STCEN0 IICRSV0 STCF0 IICC0.STT0 clear flag Generate start condition Start condition generation unsuccessful: clear STT0 flag Condition for clearing (STCF0 bit = 0) Condition for setting (STCF0 bit = 1) •...
Page 572 CHAPTER 19 I C BUS (4) IIC clock selection register 0 (IICCL0) The IICCL0 register is used to set the transfer clock for the I C0 bus. The IICCL0 register can be read or written in 8-bit or 1-bit units. However, the CLD0 and DAD0 bits are read- only.
Page 573 CHAPTER 19 I C BUS (5) IIC function expansion register 0 (IICX0) These registers set the function expansion of I C0 (valid only in high-speed mode). These registers can be read or written in 8-bit or 1-bit units. The CLX0 bit is set in combination with the IICCL0.SMC0, IICCL0.CL01, and IICCL0.CL00 bits (refer to 19.3 (6) I C0 transfer clock setting method).
Page 574 CHAPTER 19 I C BUS Table 19-2. Selection Clock Setting IICX0 IICCL0 Selection Clock Transfer Clock Settable Internal System Operation Mode Clock Frequency (f Bit 0 Bit 3 Bit 1 Bit 0 Range CLX0 SMC0 CL01 CL00 4.0 MHz to 8.38 MHz Normal mode (SMC0 bit = 0) /172...
Page 575 CHAPTER 19 I C BUS (7) IIC shift register 0 (IIC0) The IIC0 shift register is used for serial transmission/reception (shift operations) that is synchronized with the serial clock. The IIC0 shift register can be read or written in 8-bit units, but data should not be written to the IIC0 shift register during a data transfer.
Page 576: Functions
CHAPTER 19 I C BUS 19.4 Functions 19.4.1 Pin configuration The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows. SCL0 ....This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. SDA0 ....This pin is used for serial data input and output.
Page 577: I C Bus Definitions And Control Methods
CHAPTER 19 I C BUS 19.5 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the status generated by the I bus. The transfer timing for the “start condition”, “address”, “transfer direction specification”, “data”, and “stop condition”...
Page 578: Addresses
CHAPTER 19 I C BUS 19.5.2 Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines.
Page 579: Transfer Direction Specification
CHAPTER 19 I C BUS 19.5.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device.
Page 580: Ack
CHAPTER 19 I C BUS 19.5.4 ACK ACK is used to confirm the serial data status of the transmitting and receiving devices. The receiving device returns ACK for every 8 bits of data it receives. The transmitting device normally receives ACK after transmitting 8 bits of data. When ACK is returned from the receiving device, the reception is judged as normal and processing continues.
Page 581: Stop Condition
CHAPTER 19 I C BUS 19.5.5 Stop condition When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition. A stop condition is generated when serial transfer from the master device to the slave device has been completed. Stop conditions can be detected when the device is used as a slave.
Page 582: Wait State
CHAPTER 19 I C BUS 19.5.6 Wait state The wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0 pin to low level notifies the communication partner of the wait status. When wait status has been canceled for both the master and slave devices, the next data transfer can begin.
Page 583 CHAPTER 19 I C BUS Figure 19-10. Wait State (2/2) (b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKE0 = 1) Master and slave both wait Master after output of ninth clock. IIC0 data write (cancel wait) IIC0 SCL0...
Page 584: Wait State Cancellation Method
CHAPTER 19 I C BUS 19.5.7 Wait state cancellation method In the case of I C0, wait state can be canceled normally in the following ways. • By writing data to the IIC0 register • By setting the IICC0.WREL0 bit to 1 (wait state cancellation) •...
Page 585: I C Interrupt Request Signals (Intiic0)
CHAPTER 19 I C BUS 19.6 I C Interrupt Request Signals (INTIIC0) The following shows the value of the IICS0 register at the INTIIC0 interrupt request signal generation timing and at the INTIIC0 signal timing. Remark Start condition AD6 to AD0: Address R/W: Transfer direction specification ACK:...
Page 586: Master Device Operation
CHAPTER 19 I C BUS 19.6.1 Master device operation (1) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1> When IICC0.WTIM0 bit = 0 IICC0.SPT0 bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 Δ5 1: IICS0 register = 1000X110B 2: IICS0 register = 1000X000B...
Page 587 CHAPTER 19 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIM0 bit = 0 IICC0.STT0 bit = 1 SPT0 bit = 1 ↓ ↓ AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ7...
Page 588 CHAPTER 19 I C BUS (3) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIM0 bit = 0 SPT0 bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 Δ5 1: IICS0 register = 1010X110B 2: IICS0 register = 1010X000B Note 3: IICS0 register = 1010X000B (WTIM0 bit = 1...
Page 589: Slave Device Operation (When Receiving Slave Address Data (Address Match))
CHAPTER 19 I C BUS 19.6.2 Slave device operation (when receiving slave address data (address match)) (1) Start ~ Address ~ Data ~ Data ~ Stop <1> When IICC0.WTIM0 bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ4 1: IICS0 register = 0001X110B 2: IICS0 register = 0001X000B...
Page 590 CHAPTER 19 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM0 bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICS0 register = 0001X110B 2: IICS0 register = 0001X000B...
Page 591 CHAPTER 19 I C BUS (3) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIM0 bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICS0 register = 0001X110B 2: IICS0 register = 0001X000B...
Page 592 CHAPTER 19 I C BUS (4) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM0 bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ4 1: IICS0 register = 0001X110B...
Page 593: Slave Device Operation (When Receiving Extension Code)
CHAPTER 19 I C BUS 19.6.3 Slave device operation (when receiving extension code) Always under communication when receiving the extension code. (1) Start ~ Code ~ Data ~ Data ~ Stop <1> When IICC0.WTIM0 bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ4...
Page 594 CHAPTER 19 I C BUS (2) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM0 bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICS0 register = 0010X010B 2: IICS0 register = 0010X000B...
Page 595 CHAPTER 19 I C BUS (3) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIM0 bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICS0 register = 0010X010B 2: IICS0 register = 0010X000B...
Page 596 CHAPTER 19 I C BUS (4) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM0 bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ4 1: IICS0 register = 0010X010B...
Page 597: Operation Without Communication
CHAPTER 19 I C BUS 19.6.4 Operation without communication (1) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 Δ1 Δ 1: IICS0 register = 00000001B Δ: Generated only when IICC0.SPIE0 bit = 1 Remark User’s Manual U17703EJ2V0UD...
Page 598: Arbitration Loss Operation (Operation As Slave After Arbitration Loss)
CHAPTER 19 I C BUS 19.6.5 Arbitration loss operation (operation as slave after arbitration loss) When used as master in the multi-master system, check the arbitration result by reading the IICS0.MSTS0 bit for checking arbitration result by each INTIIC0 interrupt occurrence. (1) When arbitration loss occurs during transmission of slave address data <1>...
Page 599 CHAPTER 19 I C BUS (2) When arbitration loss occurs during transmission of extension code <1> When WTIM0 bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ4 1: IICS0 register = 0110X010B 2: IICS0 register = 0010X000B 3: IICS0 register = 0010X000B Δ...
Page 600: Operation When Arbitration Loss Occurs (No Communication After Arbitration Loss)
CHAPTER 19 I C BUS 19.6.6 Operation when arbitration loss occurs (no communication after arbitration loss) When used as master in the multi-master system, check the arbitration result by reading the IICS0.MSTS0 bit for checking arbitration result by each INTIIC0 interrupt occurrence. (1) When arbitration loss occurs during transmission of slave address data AD6 to AD0 D7 to D0...
Page 601 CHAPTER 19 I C BUS (3) When arbitration loss occurs during data transfer <1> When IICC0.WTIM0 bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ3 1: IICS0 register = 10001110B 2: IICS0 register = 01000000B Δ 3: IICS0 register = 00000001B Remark : Always generated Δ: Generated only when SPIE0 bit = 1...
Page 602 CHAPTER 19 I C BUS (4) When arbitration loss occurs due to restart condition during data transfer <1> Not extension code (Example: Address mismatch) AD6 to AD0 D7 to Dn AD6 to AD0 D7 to D0 Δ3 1: IICS0 register = 1000X110B 2: IICS0 register = 01000110B Δ...
Page 603 CHAPTER 19 I C BUS (5) When arbitration loss occurs due to stop condition during data transfer AD6 to AD0 D7 to Dn Δ2 1: IICS0 register = 1000X110B Δ 2: IICS0 register = 01000001B Remarks 1. : Always generated Δ: Generated only when SPIE0 bit = 1 X: don’t care 2.
Page 604 CHAPTER 19 I C BUS (6) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a restart condition <1> When WTIM0 bit = 0 IICC0.STT0 bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 Δ5...
Page 605 CHAPTER 19 I C BUS (7) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition <1> When WTIM0 bit = 0 STT0 bit = 1 ↓ AD6 to AD0 D7 to D0 Δ4 1: IICS0 register = 1000X110B 2: IICS0 register = 1000X000B (WTIM0 bit = 1) 3: IICS0 register = 1000XX00B...
Page 606 CHAPTER 19 I C BUS (8) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a stop condition <1> When WTIM0 bit = 0 IICC0.SPT0 bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 Δ5...
Page 607: Interrupt Request Signal (Intiic0) Generation Timing And Wait Control
CHAPTER 19 I C BUS 19.7 Interrupt Request Signal (INTIIC0) Generation Timing and Wait Control The setting of the IICC0.WTIM0 bit determines the timing by which the INTIIC0 signal is generated and the corresponding wait control, as shown below. Table 19-3. INTIIC0 Signal Generation Timing and Wait Control WTIM0 Bit During Slave Device Operation During Master Device Operation...
Page 608: Address Match Detection Method
CHAPTER 19 I C BUS (4) Wait cancellation method The four wait cancellation methods are as follows. • By writing data to the IIC0 register • By setting the IICC0.WREL0 bit (canceling wait state) • By setting the IICC0.STT0 bit (generating start condition) Note •...
Page 609: Extension Code
CHAPTER 19 I C BUS 19.10 Extension Code When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (EXC0) is set for extension code reception and an interrupt request signal (INTIIC0) is issued at the falling edge of the eighth clock. The local address stored in the SVA0 register is not affected.
Page 610: Arbitration
CHAPTER 19 I C BUS 19.11 Arbitration When several master devices simultaneously generate a start condition (when the IICC0.STT0 bit is set to 1 before the IICS0.STD0 bit is set to 1), communication among the master devices is performed as the number of clocks is adjusted until the data differs.
Page 611: Wakeup Function
CHAPTER 19 I C BUS Table 19-5. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 During address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission...
Page 612: Communication Reservation
CHAPTER 19 I C BUS 19.13 Communication Reservation 19.13.1 When communication reservation function is enabled (IICF0.IICRSV0 bit = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used.
Page 613 CHAPTER 19 I C BUS The communication reservation timing is shown below. Figure 19-12. Communication Reservation Timing Write STT0=1 Program processing to IIC0 Communication Hardware processing SPD0 and reservation STD0 INTIIC0 SCL0 SDA0 Generated by master with bus access IIC0: IIC shift register 0 STT0: Bit 1 of IIC control register 0 (IICC0)
Page 614 CHAPTER 19 I C BUS The communication reservation flowchart is illustrated below. Figure 19-14. Communication Reservation Flowchart STT0 = 1 ; Sets STT0 flag (communication reservation). Define communication ; Defines that communication reservation is in effect (defines and sets user flag to any part of RAM). reservation ;...
Page 615: When Communication Reservation Function Is Disabled (Iicf0.Iicrsv0 Bit = 1)
CHAPTER 19 I C BUS 19.13.2 When communication reservation function is disabled (IICF0.IICRSV0 bit = 1) When the IICC0.STT0 bit is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. The following two statuses are included in the status where bus is not used.
Page 616: Cautions
(3) When the IICC0.IICE0 bit of the V850ES/KG2 is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line. Be sure to set the IICC0.IICE0 bit to 1 when the SCL0 and SDA0 lines are high level.
Page 617: Communication Operations
This flowchart is broadly divided into the initial settings, communication waiting, and communication processing. The processing when the V850ES/KG2 looses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown.
Page 618: Master Operation In Single Master System
CHAPTER 19 I C BUS 19.15.1 Master operation in single master system Figure 19-15. Master Operation in Single Master System START Note Initialize I C bus Refer to Table 4-16 Settings When Port Pins Are Used for Alternate Functions Set ports to set the I C mode before this function is used.
Page 619: Master Operation In Multimaster System
CHAPTER 19 I C BUS 19.15.2 Master operation in multimaster system Figure 19-16. Master Operation in Multimaster System (1/3) START Refer to Table 4-16 Settings When Port Pins Are Used for Alternate Functions Set ports to set the I C mode before this function is used. IICX0 ←...
Page 620 CHAPTER 19 I C BUS Figure 19-16. Master Operation in Multimaster System (2/3) Communication reservation enabled Communication start preparation STT0 = 1 (start condition generation) Securing wait time by software Wait (refer to Table 19-6) MSTS0 = 1? INTIIC0 interrupt occurred? Waiting for bus release (communication reserved) EXC0 = 1 or COI0 =1?
Page 621 INTIIC0 interrupt occurrence to confirm the arbitration result. 3. When using the V850ES/KG2 as the slave in the multimaster system, confirm the status using the IICS0 and IICF0 registers for each INTIIC0 interrupt occurrence to determine the next processing.
Page 622: Slave Operation
CHAPTER 19 I C BUS 19.15.3 Slave operation The following shows the processing procedure of the slave operation. Basically, the operation of the slave device is event-driven. Therefore, processing by an INTIIC0 interrupt (processing requiring a significant change of the operation status, such as stop condition detection during communication) is necessary.
Page 623 CHAPTER 19 I C BUS For reception, receive the required number of data and do not return ACK for the next data immediately after transfer is complete. After that, the master device generates the stop condition or restart condition. This causes exit from communications.
Page 624 CHAPTER 19 I C BUS The following shows an example of the processing of the slave device by an INTIIC0 interrupt (it is assumed that no extension codes are used here). During an INTIIC0 interrupt, the status is confirmed and the following steps are executed.
Page 625: Timing Of Data Communication
CHAPTER 19 I C BUS 19.16 Timing of Data Communication When using I C bus mode, the master device generates an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the IICS0.TRC0 bit that specifies the data transfer direction and then starts serial communication with the slave device.
Page 626 CHAPTER 19 I C BUS Figure 19-20. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device ← ← IIC0 IIC0 address IIC0 data ACKD0 STD0 SPD0...
Page 627 CHAPTER 19 I C BUS Figure 19-20. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device ← ← IIC0 IIC0 data IIC0 data ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0...
Page 628 CHAPTER 19 I C BUS Figure 19-20. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IIC0 data IIC0 address IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0...
Page 629 CHAPTER 19 I C BUS Figure 19-21. Example of Slave to Master Communication (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (1/3) (a) Start condition ~ address Processing by master device ← ← IIC0 IIC0 address IIC0 FFH Note ACKD0...
Page 630 CHAPTER 19 I C BUS Figure 19-21. Example of Slave to Master Communication (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (2/3) (b) Data Processing by master device ← ← IIC0 IIC0 FFH Note IIC0 FFH Note ACKD0 STD0 SPD0...
Page 631 CHAPTER 19 I C BUS Figure 19-21. Example of Slave to Master Communication (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (3/3) (c) Stop condition Processing by master device ← IIC0 address ← IIC0 IIC0 FFH Note ACKD0 STD0 SPD0...
Page 632: Chapter 20 Dma Function (Dma Controller)
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) The V850ES/KG2 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and I/O, between memories, or between I/Os based on DMA requests issued by the on-chip peripheral I/O (serial interface, timer/counter, and A/D converter), interrupts from external input pins, or software triggers (memory refers to internal RAM or external memory).
Page 633: Configuration
DMA channel control register n (DCHCn) DMA addressing control register n (DADCn) DMA trigger factor Channel register n (DTFRn) control DMAC Bus interface External bus V850ES/KG2 External External External I/O Remark n = 0 to 3 User’s Manual U17703EJ2V0UD...
Page 634: Registers
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) 20.3 Registers (1) DMA source address registers 0 to 3 (DSA0 to DSA3) The DSA0 to DSA3 registers set the DMA source addresses (26 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DSAnH and DSAnL.
Page 635 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (2) DMA destination address registers 0 to 3 (DDA0 to DDA3) The DDA0 to DDA3 registers set the DMA destination address (26 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DDAnH and DDAnL. These registers can be read or written in 16-bit units.
Page 636 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (3) DMA byte count registers 0 to 3 (DBC0 to DBC3) The DBC0 to DBC3 registers are 16-bit registers that set the byte transfer count for DMA channel n (n = 0 to 3). These registers hold the remaining transfer count during DMA transfer.
Page 637 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (4) DMA addressing control registers 0 to 3 (DADC0 to DADC3) The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n = 0 to 3). These registers can be read or written in 16-bit units.
Page 638 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (5) DMA channel control registers 0 to 3 (DCHC0 to DCHC3) The DCHC0 to DCHC3 registers are 8-bit registers that control the DMA transfer operating mode for DMA channel n. These registers can be read or written in 8-bit or 1-bit units (however, bit 7 is read-only and bits 1 and 2 are write-only.
Page 639 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt request signals from on-chip peripheral I/O. The interrupt request signals set by these registers serve as DMA transfer start factors.
Page 640 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) Table 20-1. DMA Start Factors IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source DMA request by interrupt disabled INTWDTM1 INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTTM000 INTTM001 INTTM010 INTTM011 INTTM50 INTTM51 INTCSI00 INTCSI01 INTSRE0 INTSR0 INTST0...
Page 641: Transfer Targets
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) 20.4 Transfer Targets Table 20-2 shows the relationship between the transfer targets (√: Transfer enabled, ×: Transfer disabled). Table 20-2. Relationship Between Transfer Targets Transfer Destination Internal ROM On-Chip Internal RAM External Memory Peripheral I/O ×...
Page 642: Transfer Types
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) 20.6 Transfer Types As a transfer type, the 2-cycle transfer is supported. In two-cycle transfer, data transfer is performed in two cycles, a read cycle and a write cycle. In the read cycle, the transfer source address is output and reading is performed from the source to the DMAC. In the write cycle, the transfer destination address is output and writing is performed from the DMAC to the destination.
Page 643: Time Related To Dma Transfer
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) 20.8 Time Related to DMA Transfer The time required to respond to a DMA request, and the minimum number of clocks required for DMA transfer are shown below. Note 1 Single transfer: DMA response time (<1>) + Transfer source memory access (<2>) + 1 + Transfer destination memory access (<2>) DMA Cycle...
Page 644: Dma Transfer Start Factors
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) 20.9 DMA Transfer Start Factors There are two types of DMA transfer start factors, as shown below. (1) Request by software If the DCHCn.STGn bit is set to 1 while the DCHCn.TCn bit = 0 and DCHCn.Enn bit = 1 (DMA transfer enabled), DMA transfer is started.
Page 645: Dma Abort Factors
0 and TCn bit is set to 1, a DMA transfer end interrupt request signal (INTDMAn) is generated for the interrupt controller (INTC) (n = 0 to 3). The V850ES/KG2 does not output a terminal count signal to an external device. Therefore, confirm completion of DMA transfer by using the DMA transfer end interrupt or polling the TCn bit.
Page 646 Figure 20-1. Priority of DMA (1) System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit DF1 bit DF2 bit Preparation Preparation Preparation Read Write Read Write Read DMA transfer processing for transfer processing for transfer for transfer Idle Idle DMA2...
Page 647 Figure 20-2. Priority of DMA (2) System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit DF1 bit DF2 bit Preparation Preparation Preparation Read Read Write Write Read DMA transfer processing for transfer processing for transfer for transfer Idle Idle DMA0...
Page 648 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) Figure 20-3. Period in Which DMA Transfer Request Is Ignored (1) System clock DMAn transfer Note 1 request DFn bit Note 2 Note 2 Note 2 Mode of processing CPU processing DMA0 processing CPU processing Preparation Read cycle Write cycle...
Page 649 Figure 20-4. Period in Which DMA Transfer Request Is Ignored (2) System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit DF1 bit DF2 bit Preparation Preparation Preparation Read Write Read Write Read DMA transfer processing for transfer processing for transfer for transfer...
Page 650: Cautions
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) 20.13 Cautions (1) Caution for VSWC register When using the DMAC, be sure to set an appropriate value, in accordance with the operating frequency, to the VSWC register. When the default value (77H) of the VSWC register is used, or if an inappropriate value is set to the VSWC register, the operation is not correctly performed (for details of the VSWC register, refer to 3.4.8 (1) (a) System wait control register (VSWC)).
Page 651 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (4) DMA transfer initialization procedure (setting DCHCn.INITn bit to 1) Even if the INITn bit is set to 1 when the channel executing DMA transfer is to be initialized, the channel may not be initialized. To accurately initialize the channel, execute either of the following two procedures. (a) Temporarily stop transfer of all DMA channels Initialize the channel executing DMA transfer using the procedure in <1>...
Page 652 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (b) Repeatedly execute setting INITn bit until transfer is forcibly terminated correctly <1> Suppress a request from the DMA request source of the channel to be forcibly terminated (stop operation of the on-chip peripheral I/O). <2>...
Page 653 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (8) Bus arbitration for CPU Because the DMA controller has a higher priority bus mastership than the CPU, a CPU access that takes place during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the CPU.
Page 654 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (12) Read values of DSAn and DDAn registers Values in the middle of updating may be read from the DSAn and DDAn registers during DMA transfer (n = 0 to 3). For example, if the DSAnH register and then the DSAnL register are read when the DMA transfer source address (DSAn register) is 0000FFFFH and the count direction is incremental (DADCn.SAD1 and DADCn.SAD0 bits = 00), the value of the DSAnL register differs as follows, depending on whether DMA transfer is executed immediately after the DSAnH register is read.
Page 655: Chapter 21 Interrupt/Exception Processing Function
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.1 Overview The V850ES/KG2 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and realize an interrupt function that can service interrupt requests from a total of 50 sources. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 656 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 21-1. Interrupt Source List (1/2) Type Classification Default Name Trigger Interrupt Exception Handler Restored Interrupt Priority Source Code Address Control Register Reset Interrupt – RESET RESET pin input 0000H 00000000H Undefined – Internal reset input from WDT1 WDT1, WDT2 WDT2...
Page 657 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 21-1. Interrupt Source List (2/2) Type Classification Default Name Trigger Interrupt Exception Handler Restored Interrupt Priority Source Code Address Control Register Maskable Interrupt INTSRE1 UART1 reception error UART1 01B0H 000001B0H nextPC SREIC1 occurrence INTSR1 UART1 reception completion UART1 01C0H...
Page 658 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION Remarks 1. Default priority: The priority order when two or more maskable interrupt requests with the same priority level are generated at the same time. The highest priority is 0. The priority of non-maskable interrupt request is as follows. INTWDT2 >...
Page 659: Non-Maskable Interrupts
Non-maskable interrupts (NMI) are not subject to priority control and take precedence over all other interrupt request signals. The following three types of non-maskable interrupt request signals are available in the V850ES/KG2. • NMI pin input (NMI) • Non-maskable interrupt request signal (INTWDT1) due to overflow of watchdog timer 1 •...
Page 660 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 21-1. Acknowledging Non-Maskable Interrupt Request Signals (1/2) (a) If two or more NMI request signals are simultaneously generated · NMI and INTWDT1 requests simultaneously generated · NMI and INTWDT2 requests simultaneously generated Main routine Main routine INTWDT1 INTWDT2...
Page 661 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 21-1. Acknowledging Non-Maskable Interrupt Request Signals (2/2) (b) If a new non-maskable interrupt request signal is generated during a non-maskable interrupt servicing Non-maskable Non-maskable interrupt request newly generated during non-maskable interrupt servicing interrupt currently INTWDT1 INTWDT2 being serviced...
Page 662: Operation
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.2.1 Operation Upon generation of a non-maskable interrupt request signal, the CPU performs the following processing and transfers control to a handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3>...
Page 663: Restore
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.2.2 Restore Execution is restored from non-maskable interrupt servicing by the RETI instruction. (1) In case of NMI Restore from NMI processing is done with the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC.
Page 664: Np Flag
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt servicing is in progress. This flag is set when a non-maskable interrupt request has been acknowledged, and masks all non-maskable requests to prevent multiple interrupts.
Page 665: Maskable Interrupts
21.3 Maskable Interrupts Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/KG2 has 47 maskable interrupt sources (refer to 21.1.1 Features). If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority.
Page 666 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 21-4. Maskable Interrupt Servicing INT input Interrupt mask released? Priority higher than INTC acknowledged that of interrupt currently being serviced? Priority higher than that of other interrupt requests? Highest default priority of interrupt requests with the same priority? Maskable interrupt request Interrupt request pending...
Page 667: Restore
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.3.2 Restore Execution is restored from maskable interrupt servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. (1) Loads the values of the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit and the PSW.NP bit are both 0.
Page 668: Priorities Of Maskable Interrupts
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.3.3 Priorities of maskable interrupts INTC provides a multiple interrupt servicing in which an interrupt can be acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels specified by the interrupt priority level specification bit (xxICn.xxPRn bit).
Page 669 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 21-6. Example of Interrupt Nesting (1/2) Main routine Servicing of a Servicing of b Interrupt request a Interrupt request b Interrupt request b is acknowledged (level 3) (level 2) because the priority of b is higher than that of a and interrupts are enabled.
Page 670 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 21-6. Example of Interrupt Nesting (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k priority is lower than that of i.
Page 671 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 21-7. Example of Servicing Simultaneously Generated Interrupt Request Signals Main routine Interrupt request a (level 2) Note 1 Interrupt request b (level 1) ·Interrupt requests b and c are Servicing of interrupt Note 2 Interrupt request c (level 1) acknowledged first according to their request b...
Page 672: Interrupt Control Register (Xxlcn)
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.3.4 Interrupt control register (xxlCn) An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. The interrupt control registers can be read or written in 8-bit or 1-bit units. Reset sets xxICn to 47H.
Page 673 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 21-2. Interrupt Control Registers (xxlCn) (1/2) Address Register Bits <7> <6> FFFFF110H WDT1IC WDT1IF WDT1MK WDT1PR2 WDT1PR1 WDT1PR0 FFFFF112H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF114H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF116H PIC2 PIF2 PMK2 PPR22...
Page 674: Interrupt Mask Registers 0 To 3 (Imr0 To Imr3)
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 21-2. Interrupt Control Registers (xxlCn) (2/2) Address Register Bits <7> <6> FFFFF17CH DMAIC1 DMAIF1 DMAMK1 DMAPR12 DMAPR11 DMAPR10 FFFFF17EH DMAIC2 DMAIF2 DMAMK2 DMAPR22 DMAPR21 DMAPR20 FFFFF180H DMAIC3 DMAIF3 DMAMK3 DMAPR32 DMAPR31 DMAPR30 21.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) These registers set the interrupt mask status for maskable interrupts.
Page 675 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION After reset: FFFFH Address: IMR0 FFFFF100H, IMR0L FFFFF100H, IMR0H FFFFF101H Note IMR0 (IMR0H CSI0MK1 CSI0MK0 TM5MK1 TM5MK0 TM0MK11 TM0MK10 TM0MK01 TM0MK00 (IMR0L) PMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 WDT1MK After reset: FFFFH Address: IMR1 FFFFF102H, IMR1L FFFFF102H, IMR1H FFFFF103H Note IMR1 (IMR1H...
Page 676: In-Service Priority Register (Ispr)
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently being acknowledged. When the interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set (1) and remains set while the interrupt is being serviced.
Page 677: Id Flag
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.3.7 ID flag The interrupt disable flag (ID) is allocated to the PSW and controls the maskable interrupt’s operating state, and stores control information regarding enabling/disabling reception of interrupt request signals. Reset sets this flag to 00000020H. After reset: 00000020H NP EP ID SAT CY OV...
Page 678: Watchdog Timer Mode Register 1 (Wdtm1)
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.3.8 Watchdog timer mode register 1 (WDTM1) This register is a special register that can be written to only in a special sequence. To generate a maskable interrupt (INTWDT1), clear the WDTM14 bit to 0. This register can be read or written in 8-bit or 1-bit units (for details, refer to CHAPTER 12 WATCHDOG TIMER FUNCTIONS).
Page 679: External Interrupt Request Input Pins (Nmi, Intp0 To Intp7)
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.4 External Interrupt Request Input Pins (NMI, INTP0 to INTP7) 21.4.1 Noise elimination (1) Noise elimination for NMI pin The NMI pin includes a noise eliminator that operates using analog delay. Therefore, a signal input to the NMI pin is not detected as an edge unless it maintains its input level for a certain period.
Page 680 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION (a) Digital noise elimination control register (NFC) The NFC register controls elimination of noise on the INTP3 pin. If f is used as the noise elimination clock, the external interrupt function of the INTP3 pin can be used even in the IDLE/STOP mode. This register can be read or written in 8-bit or 1-bit units.
Page 681: Edge Detection
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION <Noise elimination width> The digital noise elimination width (t ) is as follows, where T is the sampling clock period and M is the WIT3 number of samplings. • t < (M − 1)T: Accurately eliminated as noise WIT3 •...
Page 682 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt rising and falling edge specification registers 0 (INTR0, INTF0) These are 8-bit registers that specify detection of the rising and falling edges of the NMI and INTP0 to INTP3 pins. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
Page 683 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) External interrupt rising and falling edge specification registers 3 (INTR3, INTF3) These are 8-bit registers that specify detection of the rising and falling edges of the INTP7 pin. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
Page 684 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) External interrupt rising and falling edge specification registers 9H (INTR9H, INTF9H) These are 8-bit registers that specify detection of the rising edge of the INTP4 to INTP6 pins. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
Page 685: Software Exceptions
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.5 Software Exceptions A software exception is generated when the CPU executes the TRAP instruction. Software exceptions can always be acknowledged. 21.5.1 Operation If a software exception occurs, the CPU performs the following processing and transfers control to a handler routine.
Page 686: Restore
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.5.2 Restore Execution is restored from software exception processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. <1>...
Page 687: Ep Flag
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.5.3 EP flag The EP flag is a status flag that indicates that exception processing is in progress. It is set when an exception occurs. After reset: 00000020H NP EP ID SAT CY OV Exception processing status Exception processing not in progress Exception processing in progress User’s Manual U17703EJ2V0UD...
Page 688: Exception Trap
21.6 Exception Trap The exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/KG2, an illegal opcode trap (ILGOP: illegal opcode trap) is considered as an exception trap. 21.6.1 Illegal opcode An illegal opcode is defined as an instruction with instruction opcode (bits 10 to 5) = 111111B, sub-opcode (bits 26 to 23) = 0111B to 1111B, and sub-opcode (bit 16) = 0B.
Page 689 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 21-10. Exception Trap Processing Exception trap (ILGOP) occurs DBPC Restored PC DBPSW PSW.NP PSW.EP CPU processing PSW.ID 00000060H Exception processing (2) Restore Execution is restored from exception trap processing by the DBRET instruction. When the DBRET instruction is executed, the CPU performs the following processing and transfers control to the address of the restored <1>...
Page 690: Debug Trap
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.6.2 Debug trap A debug trap is an exception that occurs upon execution of the DBTRAP instruction and that can be acknowledged at all times. When a debug trap occurs, the CPU performs the following processing. (1) Operation <1>...
Page 691 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restore Execution is restored from debug trap processing by the DBRET instruction. When the DBRET instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. <1>...
Page 692: Multiple Interrupt Servicing Control
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.7 Multiple Interrupt Servicing Control Multiple interrupt servicing control is a function that stops an interrupt service routine currently in progress if a higher priority interrupt request signal is generated, and processes the acknowledgment operation of the higher priority interrupt request signal.
Page 693 CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) To generate exception in service program Service program for maskable interrupt or exception … … • EIPC saved to memory or register • EIPSW saved to memory or register … • TRAP instruction ←Acknowledges exceptions such as TRAP instruction. …...
Page 694: Interrupt Response Time
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.8 Interrupt Response Time Except in the following cases, the CPU interrupt response time is a minimum of 4 clocks. If inputting consecutive interrupt request signals, at least 4 clocks must be placed between each interrupt request signal. •...
Page 695: Periods In Which Interrupts Are Not Acknowledged By Cpu
CHAPTER 21 INTERRUPT/EXCEPTION PROCESSING FUNCTION 21.9 Periods in Which Interrupts Are Not Acknowledged by CPU Interrupts are acknowledged by the CPU while an instruction is being executed. However, no interrupt is acknowledged between an interrupt request non-sample instruction and the next instruction. The following instructions are interrupt request non-sample instructions.
Page 696: Chapter 22 Key Interrupt Function
CHAPTER 22 KEY INTERRUPT FUNCTION 22.1 Function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the KRM register. Caution If any of the KR0 to KR7 pins is at low level, the INTKR signal is not generated even if a falling edge is input to another pin.
Page 697: Register
CHAPTER 22 KEY INTERRUPT FUNCTION 22.2 Register (1) Key return mode register (KRM) The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 698: Chapter 23 Standby Function
CHAPTER 23 STANDBY FUNCTION 23.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 23-1. Table 23-1.
Page 699 CHAPTER 23 STANDBY FUNCTION Figure 23-1. Status Transition (1/2) Normal operation mode (operation with main clock) End of oscillation End of oscillation stabilization time count stabilization time count Note 3 Setting of HALT mode Interrupt request End of oscillation stabilization time count Wait for stabilization Wait for stabilization of oscillation...
Page 700 CHAPTER 23 STANDBY FUNCTION Figure 23-1. Status Transition (2/2) Normal operation mode (operation with main clock) End of oscillation End of oscillation stabilization time count stabilization time count Setting of subclock operation mode Wait for stabilization Wait for stabilization of oscillation of oscillation Setting of normal operation mode...
Page 701: Registers
CHAPTER 23 STANDBY FUNCTION 23.2 Registers (1) Power save control register (PSC) This is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the standby mode. The PSC register is a special register that can be written to only in a special sequence (refer to 3.4.7 Special registers).
Page 702 CHAPTER 23 STANDBY FUNCTION (2) Power save mode register (PSMR) This is an 8-bit register that controls the operation status in the standby mode and the clock operation. This register can be read or written in 8-bit or 1-bit units. Reset sets PSMR to 00H.
Page 703 CHAPTER 23 STANDBY FUNCTION (3) Oscillation stabilization time selection register (OSTS) The wait time until the oscillation stabilizes after the STOP mode is released is controlled by the OSTS register. The OSTS register can be read or written in 8-bit units. Reset sets OSTS to 01H.
Page 704: Halt Mode
CHAPTER 23 STANDBY FUNCTION 23.3 HALT Mode 23.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues.
Page 705 CHAPTER 23 STANDBY FUNCTION Table 23-3. Operation Status in HALT Mode Setting of HALT Mode When CPU Is Operating with Main Clock Item When Subclock Is Not Used When Subclock Is Used Stops operation Main clock oscillator Oscillation enabled − Subclock oscillator Oscillation enabled Interrupt controller...
Page 706: Idle Mode
CHAPTER 23 STANDBY FUNCTION 23.4 IDLE Mode 23.4.1 Setting and operation status The IDLE mode is set by clearing the PSMR.PSM bit to 0 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE mode, the clock oscillator continues operation but clock supply to the CPU and other on-chip peripheral functions stops.
Page 707: Releasing Idle Mode
CHAPTER 23 STANDBY FUNCTION 23.4.2 Releasing IDLE mode The IDLE mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal (when the CPU is operating on the subclock)), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the IDLE mode, or reset (RESET pin input, WDTRES2 signal (when the CPU is operating on the subclock)).
Page 708 CHAPTER 23 STANDBY FUNCTION Table 23-5. Operation Status in IDLE Mode Setting of IDLE Mode When CPU Is Operating with Main Clock Item When Subclock Is Not Used When Subclock Is Used Stops operation Main clock oscillator Oscillation enabled − Subclock oscillator Oscillation enabled Interrupt controller...
Page 709: Stop Mode
CHAPTER 23 STANDBY FUNCTION 23.5 STOP Mode 23.5.1 Setting and operation status The STOP mode is set when the PSMR.PSM bit is set to 1 and the PSC.STP bit is set to 1 in the normal operation mode. In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops. Clock supply to the CPU and the on-chip peripheral functions is stopped.
Page 710: Releasing Stop Mode
CHAPTER 23 STANDBY FUNCTION 23.5.2 Releasing STOP mode The STOP mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal (when the CPU is operating on the subclock)), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the STOP mode, or reset (RESET pin input, WDTRES2 signal (when the CPU is operating on the subclock)).
Page 711 CHAPTER 23 STANDBY FUNCTION Table 23-7. Operation Status in STOP Mode Setting of STOP Mode When CPU Is Operating with Main Clock Item When Subclock Is Not Used When Subclock Is Used Stops operation Main clock oscillator Oscillation stops − Subclock oscillator Oscillation enabled Interrupt controller...
Page 712: Securing Oscillation Stabilization Time When Stop Mode Is Released
CHAPTER 23 STANDBY FUNCTION 23.5.3 Securing oscillation stabilization time when STOP mode is released When the STOP mode is released, only the oscillation stabilization time set by the OSTS register elapses. If the STOP mode has been released by reset, however, the reset value of the OSTS register, 2 (8.192 ms at f MHz) elapses.
Page 713: Subclock Operation Mode
CHAPTER 23 STANDBY FUNCTION 23.6 Subclock Operation Mode 23.6.1 Setting and operation status The subclock operation mode is set when the PCC.CK3 bit is set to 1 in the normal operation mode. When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. When the PCC.MCK bit is set to 1, the operation of the main clock oscillator is stopped.
Page 714 CHAPTER 23 STANDBY FUNCTION Table 23-8. Operation Status in Subclock Operation Mode Setting of Subclock Operation Operation Status Item Mode When Main Clock Is Oscillating When Main Clock Is Stopped Operable Subclock oscillator Oscillation enabled Interrupt controller Operable Timer P (TMP0) Operable Stops operation 16-bit timers (TM00 to TM03)
Page 715: Sub-Idle Mode
CHAPTER 23 STANDBY FUNCTION 23.7 Sub-IDLE Mode 23.7.1 Setting and operation status The sub-IDLE mode is set when the PSMR.PSM bit is cleared to 0 and the PSC.STP bit is set to 1 in the subclock operation mode. In this mode, the clock oscillator continues operation but clock supply to the CPU and the other on-chip peripheral functions is stopped.
Page 716: Releasing Sub-Idle Mode
CHAPTER 23 STANDBY FUNCTION 23.7.2 Releasing sub-IDLE mode The sub-IDLE mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal (when the CPU is operating on the subclock)), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the sub-IDLE mode, or reset (RESET pin input, WDTRES2 signal (when the CPU is operating on the subclock)).
Page 717 CHAPTER 23 STANDBY FUNCTION Table 23-10. Operation Status in Sub-IDLE Mode Setting of Sub-IDLE Operation Status Item Mode When Main Clock Is Oscillating When Main Clock Is Stopped Stops operation Subclock oscillator Oscillation enabled Interrupt controller Stops operation Timer P (TMP0) Stops operation 16-bit timers (TM00 to TM03) TM00, TM02, TM03: Stop operation...
Page 718: Chapter 24 Reset Function
CHAPTER 24 RESET FUNCTION 24.1 Overview The following reset functions are available. • Reset function by RESET pin input • Reset function by overflow of watchdog timer 1 (WDTRES1) • Reset function by overflow of watchdog timer 2 (WDTRES2) If the RESET pin goes high, the reset status is released, and the CPU starts executing the program. Initialize the contents of each register in the program as necessary.
Page 719: Operation
CHAPTER 24 RESET FUNCTION 24.3 Operation The system is reset, initializing each hardware unit, when a low level is input to the RESET pin or if watchdog timer 1 or watchdog timer 2 overflows (WDTRES1 or WDTRES2). While a low level is being input to the RESET pin, the main clock oscillator stops. Therefore, the overall power consumption of the system can be reduced.
Page 720 CHAPTER 24 RESET FUNCTION Table 24-1. Hardware Status on RESET Pin Input or Occurrence of WDTRES2 Signal Item During Reset After Reset Main clock oscillator (f Oscillation stops Oscillation starts Subclock oscillator (f Oscillation continues Peripheral clock (f to f /1024) Operation stops Operation starts after securing oscillation...
Page 721 CHAPTER 24 RESET FUNCTION Figure 24-2. Hardware Status on RESET Input Initialized to f /8 operation RESET Analog delay Analog Analog delay Analog (eliminated as noise) delay (eliminated as noise) delay Internal system reset signal Oscillation stabilization time count Overflow of timer for oscillation stabilization Figure 24-3.
Page 722 CHAPTER 24 RESET FUNCTION Figure 24-4. Timing of Reset Operation by Watchdog Timer 1 Initialized to f /8 operation WDTRES1 signal (active low) Internal system reset signal (active low) : 12-clock width Figure 24-5. Timing of Reset Operation by Watchdog Timer 2 Initialized to f /8 operation WDTRES2 signal...
Page 723: Chapter 25 Regulator
CHAPTER 25 REGULATOR 25.1 Overview The V850ES/KG2 includes a regulator to reduce the power consumption and noise. This regulator supplies a stepped-down V power supply voltage to the oscillator block and internal logic circuits (except the A/D converter, D/A converter, and output buffer). The regulator output voltage is set to 3.6 V (TYP.).
Page 724 CHAPTER 25 REGULATOR Figure 25-2. REGC Pin Connection (a) When REGC = V Input voltage = 2.7 to 5.5 V Voltage supply to oscillator/internal logic = 2.7 to 5.5 V REGC (b) When connecting REGC pin to V via a capacitor Input voltage = 4.0 to 5.5 V Voltage supply to oscillator/internal logic = 3.6 V REGC...
Page 725: Chapter 26 Flash Memory
Flash memory versions are commonly used in the following development environments and mass production applications. For altering software after the V850ES/KG2 is soldered onto the target system. For data adjustment when starting mass production. For differentiating software according to the specification in small scale production of various models.
Page 726: Memory Configuration
CHAPTER 26 FLASH MEMORY 26.2 Memory Configuration The 256/128 KB internal flash memory area is divided into 128/64 blocks and can be programmed/erased in block units. All the blocks can also be erased at once. When the boot swap function is used, the physical memory (blocks 0 to 3) located at the addresses of boot area 0 is replaced by the physical memory (blocks 4 to 7) located at the addresses of boot area 1.
Page 727: Functional Outline
CHAPTER 26 FLASH MEMORY 26.3 Functional Outline The internal flash memory of the V850ES/KG2 can be rewritten by using the rewrite function of the dedicated flash programmer, regardless of whether the V850ES/KG2 has already been mounted on the target system or not (on- board/off-board programming).
Page 728 CHAPTER 26 FLASH MEMORY Table 26-2. Basic Functions Support ( : Supported, ×: Not supported) Function Functional Outline On-Board/Off-Board Self Programming Programming Block erasure The contents of specified memory blocks are erased. × Chip erasure The contents of the entire memory area are erased all at once.
Page 729 CHAPTER 26 FLASH MEMORY Table 26-4. Security Setting <R> Function Erase, Write, Read Operations When Each Security Is Set Notes on Security Setting (√: Executable, ×: Not Executable, −: Not Supported) On-Board/ Self Programming On-Board/ Self Off-Board Programming Programming Off-Board Programming Block erase command: ×...
Page 730 CHAPTER 26 FLASH MEMORY (1) Security setting by PG-FP4 (Security flag settings) <R> When disabling the read command (Disable Read), to raise the security level, it is recommended to also disable the block erase command (Disable Block Erase) and program command (Disable Program). Furthermore, when rewriting program is not necessary similarly to the mask ROM versions, additionally disable the chip erase command (Disable Chip Erase).
Page 731: Rewriting By Dedicated Flash Programmer
26.4 Rewriting by Dedicated Flash Programmer The flash memory can be rewritten by using a dedicated flash programmer after the V850ES/KG2 is mounted on the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (FA series).
Page 732: Communication Mode
CHAPTER 26 FLASH MEMORY 26.4.2 Communication mode Communication between the dedicated flash programmer and the V850ES/KG2 is performed by serial communication using the UART0 or CSI00 interfaces of the V850ES/KG2. (1) UART0 Transfer rate: 9,600 to 153,600 bps Figure 26-3. Communication with Dedicated Flash Programmer (UART0)
Page 733 SCK00 PCM0 The dedicated flash programmer outputs the transfer clock, and the V850ES/KG2 operates as a slave. When the PG-FP4 is used as the dedicated flash programmer, it generates the following signals to the V850ES/KG2. For details, refer to the PG-FP4 User’s Manual (U15260E).
Page 734 CHAPTER 26 FLASH MEMORY Table 26-6. Wiring Between V850ES/KG2 and PG-FP4 Pin Configuration of Flash Programmer (PG-FP4) Pin Name on With CSI00-HS With CSI00 With UART0 FA Board Signal Name Pin Function Pin Name Pin No. Pin Name Pin No.
Page 735 CHAPTER 26 FLASH MEMORY Figure 26-6. Wiring Example of V850ES/KG2 Flash Writing Adapter (FA-100GC-8EU-A) (1/2) 70 69 Note 1 μ PD70F3731, μ PD70F3732 Connect to GND. Connect to VDD. Note 4 Note 2 Note 3 9 10 11 12 13 14...
Page 736 CHAPTER 26 FLASH MEMORY Figure 26-6. Wiring Example of V850ES/KG2 Flash Writing Adapter (FA-100GC-8EU-A) (2/2) Notes 1. Wire the FLMD1 pin as shown in the figure, or connect it to GND on board via a pull-down resistor. 2. Be sure to connect the REGC pin in either of the following ways.
Page 737 CHAPTER 26 FLASH MEMORY Figure 26-7. Wiring Example of V850ES/KG2 Flash Writing Adapter (FA-100GC-3BA-A) (1/2) Note 1 Connected to GND. Connected to VDD. μ PD70F3731, μ PD70F3732 Note 3 Note 4 Note 2 10 11 12 13 15 16 25 26 27 28...
Page 738 CHAPTER 26 FLASH MEMORY Figure 26-7. Wiring Example of V850ES/KG2 Flash Writing Adapter (FA-100GC-3BA-A) (2/2) Notes 1. Wire the FLMD1 pin as shown in the figure, or connect it to GND on board via a pull-down resistor. 2. Be sure to connect the REGC pin in either of the following ways.
Page 739: Flash Memory Control
CHAPTER 26 FLASH MEMORY 26.4.3 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 26-8. Procedure for Manipulating Flash Memory Start Switch to flash memory Supplies FLMD0 pulse programming mode Select communication system Manipulate flash memory End? User’s Manual U17703EJ2V0UD...
Page 740: Selection Of Communication Mode
26.4.4 Selection of communication mode In the V850ES/KG2, the communication mode is selected by inputting pulses (11 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer.
Page 741: Communication Commands
Response command Dedicated flash programmer V850ES/KG2 The following shows the commands for flash memory control in the V850ES/KG2. All of these commands are issued from the dedicated flash programmer, and the V850ES/KG2 performs the processing corresponding to the commands. Table 26-7. Flash Memory Control Commands...
Page 742: Pin Connection
FLMD0 pin via port control, etc., before writing to the flash memory. For details, refer to 26.5.5 (1) FLMD0 pin. Figure 26-11. FLMD0 Pin Connection Example V850ES/KG2 Dedicated flash programmer connection pin FLMD0 Pull-down resistor (R FLMD0 User’s Manual U17703EJ2V0UD...
Page 743 0 V must be input to the FLMD1 pin. The following shows an example of the connection of the FLMD1 pin. Figure 26-12. FLMD1 Pin Connection Example V850ES/KG2 FLMD1 Other device...
Page 744 (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. Figure 26-13. Conflict of Signals (Serial Interface Input Pin) V850ES/KG2 Dedicated flash programmer connection pins...
Page 745 V850ES/KG2 Dedicated flash programmer connection pin Other device Input pin In the flash memory programming mode, if the signal the V850ES/KG2 outputs affects the other device, isolate the signal on the other device side. V850ES/KG2 Dedicated flash programmer connection pin...
Page 746: Reset Pin
When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the dedicated flash programmer. Figure 26-15. Conflict of Signals (RESET Pin) V850ES/KG2 Dedicated flash programmer connection pin Conflict of signals...
Page 747: Rewriting By Self Programming
26.5.1 Overview The V850ES/KG2 supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. By using this interface and a self programming library that is used to rewrite the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal RAM or external memory.
Page 748: Features
(1) Secure self programming (boot swap function) The V850ES/KG2 supports a boot swap function that can exchange the physical memory (blocks 0 to 3) of boot area 0 with the physical memory (blocks 4 to 7) of boot area 1. By writing the start program to be...
Page 749: Standard Self Programming Flow
CHAPTER 26 FLASH MEMORY 26.5.3 Standard self programming flow The entire processing to rewrite the flash memory by flash self programming is illustrated below. Figure 26-18. Standard Self Programming Flow (a) Rewriting at once (b) Rewriting in block units Flash memory manipulation Flash memory manipulation Flash environment Flash environment...
Page 750: Flash Functions
Remark For details, refer to the V850 Series Flash Memory Self Programming (Single Power Supply Flash Memory) User’s Manual. Contact an NEC Electronics sales representative for the above manual. 26.5.5 Pin processing (1) FLMD0 pin The FLMD0 pin is used to set the operation mode when reset is released and to protect the flash memory from being written during self rewriting.
Page 751: Internal Resources Used
When using TM50 and TM51 after self programming, set them again. Remark For details, refer to the V850 Series Flash Memory Self Programming (Single Power Supply Flash Memory) User’s Manual. Contact an NEC Electronics sales representative for the above manual. User’s Manual U17703EJ2V0UD...
Page 752: Chapter 27 On-Chip Debug Function
The V850ES/KG2 utilizes user resources to implement an on-chip debug function by MINICUBE The V850ES/KG2 is not provided with a DCU (Debug Control Unit). However, it can be used as a simplified in- circuit emulator by using the on-chip debug emulator (MINICUBE) and debug adapter (QB-V850ESKX1H-DA). For the connection, refer to APPENDIX A DEVELOPMENT TOOLS.
Page 753: Debugging Without Using Dcu
1 kΩ RESET signal Reset circuit Notes 1. Connect TXD0/SO00 (transmit side) of the V850ES/KG2 to RXD/SI (receive side) of the target connector, and TXD/SO (transmit side) of the target connector to RXD0/SI00 (receive side) of the V850ES/KG2. 2. This pin may be used to supply a clock from MINICUBE2 during flash memory programming. For details, refer to CHAPTER 26 FLASH MEMORY.
Page 754 Not needed Not needed Not needed RESET_OUT Output Reset output pin to V850ES/KG2 RESET RESET FLMD0 Output Output pin to set V850ES/KG2 to debug mode FLMD0 FLMD0 or programming mode FLMD1 Output Output pin to set programming mode PDL5/AD5/ PDL5/AD5/...
Page 755: Maskable Functions
CHAPTER 27 ON-CHIP DEBUG FUNCTION 27.1.2 Maskable functions Only reset signals can be masked. The maskable functions with the debugger (ID850QB) and the corresponding V850ES/KG2 functions are listed below. Table 27-3. Maskable Functions Maskable Functions with ID850QB Corresponding V850ES/KG2 Functions −...
Page 756: Securing Of User Resources
CHAPTER 27 ON-CHIP DEBUG FUNCTION 27.1.3 Securing of user resources The user must prepare the following to perform communication between MINICUBE2 and the target device and implement each debug function. These items need to be set in the user program or using the compiler options. (1) Securement of memory space The shaded portions in Figure 27-2 are the areas reserved for placing the debug monitor program, so user programs and data cannot be allocated in these spaces.
Page 757 CHAPTER 27 ON-CHIP DEBUG FUNCTION (2) Reset vector A reset vector includes the jump instruction for the debug monitor program. [How to secure areas] It is not necessary to secure this area intentionally. When downloading a program, however, the debugger rewrites the reset vector in accordance with the following cases.
Page 758 To avoid problems that may occur during the debugger startup, however, it is recommended to secure this area in advance, using the compiler. The following shows examples for securing the area, using the NEC Electronics compiler CA850. Add the assemble source file and link directive code, as shown below.
Page 759 CHAPTER 27 ON-CHIP DEBUG FUNCTION (4) Securement of communication serial interface UART0 or CSI00 is used for communication between MINICUBE2 and the target system. The settings related to the serial interface modes are performed by the debug monitor program, but if the setting is changed by the user program, a communication error may occur.
Page 760 CHAPTER 27 ON-CHIP DEBUG FUNCTION • Port registers when CSI00 is used When CSI00 is used, port registers are set to make the SI00, SO00, SCK00, and HS (PMC0) pins valid by the debug monitor program. Do not change the following register settings with the user program during debugging.
Page 761: Cautions
CHAPTER 27 ON-CHIP DEBUG FUNCTION 27.1.4 Cautions (1) Handling of device that was used for debugging Do not mount a device that was used for debugging on a mass-produced product, because the flash memory was rewritten during debugging and the number of rewrites of the flash memory cannot be guaranteed. Moreover, do not embed the debug monitor program into mass-produced products.
Page 762: Rom Security Function
27.2 ROM Security Function 27.2.1 Security ID The flash memory versions of the V850ES/KG2 perform authentication using a 10-byte ID code to prevent the contents of the flash memory from being read by an unauthorized person during on-chip debugging by the on-chip debug emulator.
Page 763: Setting
CHAPTER 27 ON-CHIP DEBUG FUNCTION 27.2.2 Setting The following shows how to set the ID code as shown in Table 27-4. When the ID code is set as shown in Table 27-4, the ID code input in the configuration dialog box of the ID850QB is “123456789ABCDEF123D4”...
Page 764 CHAPTER 27 ON-CHIP DEBUG FUNCTION [Program example (when using CA850 Ver. 3.10 or later)] #-------------------------------------- SECURITYID #-------------------------------------- .section "SECURITY_ID" --Interrupt handler address 0x70 .word 0x78563412 --0-3 byte code .word 0xF1DEBC9A --4-7 byte code .hword 0xD423 --8-9 byte code Remark Add the above program example to the startup files. User’s Manual U17703EJ2V0UD...
Page 765: Chapter 28 Electrical Specifications
CHAPTER 28 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) (1/2) Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage = EV = AV REF0 ≤ V −0.3 to V Note + 0.3 −0.3 to +6.5 = EV = AV REF0 −0.3 to +6.5 = EV...
Page 766 CHAPTER 28 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit Output current, low Note Per pin P36 to P39 P00 to P06, P30 to P39, P40 to P42 Total of all pins: P50 to P55, P90 to P915 70 mA PCM0 to PCM3, PCS0, PCS1, Total of all...
Page 767: Pll Characteristics
CHAPTER 28 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V PLL Characteristics (T = 2.7 to 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input frequency Output frequency μ Lock time After V reaches 2.7 V (MIN.) Operating Conditions = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤...
Page 768 CHAPTER 28 ELECTRICAL SPECIFICATIONS Operating Conditions for EEPROM Emulation = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV REF0 REF1 = AV = 0 V, C = 50 pF)
Page 769: Main Clock Oscillator Characteristics
CHAPTER 28 ELECTRICAL SPECIFICATIONS Main Clock Oscillator Characteristics = −40 to +85°C, V (1) Crystal resonator, ceramic resonator (T = 2.7 to 5.5 V, V = 0 V) Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Oscillation In PLL mode REGC = V = 4.5 to 5.5 V frequency...
Page 770 CHAPTER 28 ELECTRICAL SPECIFICATIONS Subclock Oscillator Characteristics = −40 to +85°C, V (1) Crystal resonator (T = 2.7 to 5.5 V, V = 0 V) Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Oscillation 32.768 frequency Note 1 Oscillation stabilization Note 2 time Notes 1.
Page 771 CHAPTER 28 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV = BV REF0 REF1 = 0 V) (1/4) Parameter Symbol Conditions...
Page 772 CHAPTER 28 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV = BV REF0 REF1 = 0 V) (2/4) Parameter Symbol Conditions...
Page 773 CHAPTER 28 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV = BV REF0 REF1 = 0 V) (3/4) Parameter Symbol Conditions...
Page 774 CHAPTER 28 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV = BV REF0 REF1 = 0 V) (4/4) Note 2 Parameter Symbol...
Page 775: Data Retention Characteristics
CHAPTER 28 ELECTRICAL SPECIFICATIONS Data Retention Characteristics = −40 to +85°C) STOP Mode (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention voltage STOP mode DDDR μ STOP release signal input time DREL Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated operating range.
Page 776 CHAPTER 28 ELECTRICAL SPECIFICATIONS AC Characteristics AC Test Input Measurement Points (V , AV , EV REF0 Measurement points AC Test Output Measurement Points Measurement points Load Conditions (Device under measurement) = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
Page 777: Clock Timing
CHAPTER 28 ELECTRICAL SPECIFICATIONS CLKOUT Output Timing = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV REF0 REF1 = AV = 0 V, C = 50 pF) Parameter...
Page 778 CHAPTER 28 ELECTRICAL SPECIFICATIONS Bus Timing (1) In multiplex bus mode (a) Read/write cycle (CLKOUT asynchronous) = −40 to +85°C, V = 4.0 to 5.5 V, 4.0 V ≤ BV ≤ V , 4.0 V ≤ AV ≤ V = EV = AV = EV REF0...
Page 779 CHAPTER 28 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV REF0 REF1 = AV = 0 V, C = 50 pF) (2/2) Parameter Symbol...
Page 780 CHAPTER 28 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Asynchronous): In Multiplex Bus Mode CLKOUT (output) A16 to A21 (output) CS0, CS1 (output) <9> Hi-Z AD0 to AD15 (I/O) Address Data <6> <7> <12> ASTB (output) <17> <14> <8> <13> <11> <10> <15>...
Page 781 CHAPTER 28 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Asynchronous): In Multiplex Bus Mode CLKOUT (output) A16 to A21 (output) CS0, CS1 (output) AD0 to AD15 (I/O) Address Data <6> <7> ASTB (output) <17> <18> <14> <11> <19> <20> WR0 (output), WR1 (output) <16>...
Page 782 CHAPTER 28 ELECTRICAL SPECIFICATIONS (b) Read/write cycle (CLKOUT synchronous): In multiplex bus mode = −40 to +85°C, V = 4.0 to 5.5 V, 4.0 V ≤ BV ≤ V , 4.0 V ≤ AV ≤ V = EV = AV = EV REF0 REF1...
Page 783 CHAPTER 28 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Synchronous): In Multiplex Bus Mode CLKOUT (output) <29> A16 to A21 (output) CS0, CS1 (output) <33> <34> <30> Hi-Z AD0 to AD15 (I/O) Address Data <31> <31> ASTB (output) <32> <32> RD (output) WAIT (input) <36>...
Page 784 CHAPTER 28 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Synchronous): In Multiplex Bus Mode CLKOUT (output) <29> A16 to A21 (output) CS0, CS1 (output) <35> AD0 to AD15 (I/O) Address Data <31> <31> ASTB (output) WR0 (output), WR1 (output) <32> <32> WAIT (input) <36>...
Page 785 CHAPTER 28 ELECTRICAL SPECIFICATIONS (2) In separate bus mode (a) Read cycle (CLKOUT asynchronous): In separate bus mode = −40 to +85°C, V = 4.0 to 5.5 V, 4.0 V ≤ BV ≤ V , 4.0 V ≤ AV ≤ V = EV = AV = EV...
Page 786 CHAPTER 28 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV REF0 REF1 = AV = 0 V, C = 50 pF) (2/2) Parameter Symbol...
Page 787 CHAPTER 28 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Asynchronous): In Separate Bus Mode CLKOUT (output) CS0, CS1 (output) A0 to A21 (output) <39> <43> Hi-Z Hi-Z AD0 to AD15 (I/O) <42> <38> <41> <40> (output) <47> <45> <46> <44> WAIT (input) <48>...
Page 788 CHAPTER 28 ELECTRICAL SPECIFICATIONS (b) Write cycle (CLKOUT asynchronous): In separate bus mode = −40 to +85°C, V = 4.0 to 5.5 V, 4.0 V ≤ BV ≤ V , 4.0 V ≤ AV ≤ V = EV = AV = EV REF0 REF1...
Page 789 CHAPTER 28 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV REF0 REF1 = AV = 0 V, C = 50 pF) (2/2) Parameter Symbol...
Page 790 CHAPTER 28 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Asynchronous): In Separate Bus Mode CLKOUT (output) CS0, CS1 (output) A0 to A21 (output) <53> <58> Hi-Z Hi-Z AD0 to AD15 (I/O) <55> <57> <52> <56> <54> WR0, WR1 (output) <62> <60> <59> <61>...
Page 791 CHAPTER 28 ELECTRICAL SPECIFICATIONS (c) Read cycle (CLKOUT synchronous): In separate bus mode = −40 to +85°C, V = 4.0 to 5.5 V, 4.0 V ≤ BV ≤ V , 4.0 V ≤ AV ≤ V = EV = AV = EV REF0 REF1...
Page 792 CHAPTER 28 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Synchronous, 1 Wait): In Separate Bus Mode CLKOUT (output) <67> <67> CS0, CS1 (output) A0 to A21 (output) <68> <69> Hi-Z Hi-Z AD0 to AD15 (I/O) <70> <70> (output) <71> <72> <71> <72> WAIT (input) Remark WR0 and WR1 are high level.
Page 793 CHAPTER 28 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous): In separate bus mode = −40 to +85°C, V = 4.0 to 5.5 V, 4.0 V ≤ BV ≤ V , 4.0 V ≤ AV ≤ V = EV = AV = EV REF0 REF1...
Page 794 CHAPTER 28 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Synchronous): In Separate Bus Mode CLKOUT (output) <73> <73> CS0, CS1 (output) A0 to A21 (output) <74> <74> Hi-Z Hi-Z AD0 to AD15 (I/O) <75> <75> WR0, WR1 (output) <76> <77> <76> <77> WAIT (input) Remark RD is high level.
Page 795 CHAPTER 28 ELECTRICAL SPECIFICATIONS (3) Bus hold (a) CLKOUT asynchronous = −40 to +85°C, V = 4.0 to 5.5 V, 4.0 V ≤ BV ≤ V , 4.0 V ≤ AV ≤ V = EV = AV = EV REF0 REF1 = AV = 0 V, C...
Page 796 CHAPTER 28 ELECTRICAL SPECIFICATIONS Bus Hold (CLKOUT Asynchronous) CLKOUT (output) <78> HLDRQ (input) <81> <82> HLDAK (output) <80> <79> Address bus (output) Hi-Z Data bus (I/O) Hi-Z CS0, CS1 (output) Hi-Z ASTB (output) Hi-Z RD (output), WR0 (output), WR1 (output) User’s Manual U17703EJ2V0UD...
Page 797 CHAPTER 28 ELECTRICAL SPECIFICATIONS (b) CLKOUT synchronous = −40 to +85°C, V = 4.0 to 5.5 V, 4.0 V ≤ BV ≤ V , 4.0 V ≤ AV ≤ V = EV = AV = EV REF0 REF1 = AV = 0 V, C = 50 pF) (1/2) Parameter...
Page 798 CHAPTER 28 ELECTRICAL SPECIFICATIONS Bus Hold (CLKOUT Synchronous) CLKOUT (output) <83> <83> <84> HLDRQ (input) <86> <86> HLDAK (output) <85> Address bus (output) Hi-Z Data bus (I/O) Hi-Z CS0, CS1 (output) Hi-Z ASTB (output) Hi-Z RD (output), WR0 (output), WR1 (output) User’s Manual U17703EJ2V0UD...
Page 799 CHAPTER 28 ELECTRICAL SPECIFICATIONS Basic Operation (1) Reset/external interrupt timing = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV = BV REF0 REF1 = 0 V, C...
Page 800 CHAPTER 28 ELECTRICAL SPECIFICATIONS Reset/Interrupt <88> <87> RESET (Input) <89>/<91>/<93> <90>/<92>/<94> NMI (Input) INTPn (Input) ADTRG (Input) Remark n = 0 to 7 User’s Manual U17703EJ2V0UD...
Page 801: Timer Input Timing
CHAPTER 28 ELECTRICAL SPECIFICATIONS Timer Timing = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV = BV REF0 REF1 = 0 V, C = 50 pF) Parameter Symbol...
Page 802: Uart Timing
CHAPTER 28 ELECTRICAL SPECIFICATIONS UART Timing = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV REF0 REF1 = AV = 0 V, C = 50 pF) Parameter Symbol...
Page 803: Master Mode
CHAPTER 28 ELECTRICAL SPECIFICATIONS CSI0 Timing (1) Master mode = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV REF0 REF1 = AV = 0 V, C = 50 pF)
Page 804 CHAPTER 28 ELECTRICAL SPECIFICATIONS (a) CSICn.CKPn, DAPn bits = 00 or 11 <101> <102> <102> SCK0n (I/O) <103> <104> Hi-Z Hi-Z SI0n (input) Input data <105> Output data SO0n (output) (b) CSICn.CKPn, DAPn bits = 01 or 10 <101> <102> <102>...
Page 805 CHAPTER 28 ELECTRICAL SPECIFICATIONS CSIA Timing (1) Master mode = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV REF0 REF1 = AV = 0 V, C = 50 pF)
Page 806 CHAPTER 28 ELECTRICAL SPECIFICATIONS <106> <107> <107> SCKAn (I/O) <108> <109> Hi-Z Hi-Z SIAn (input) Input data <110> Output data SOAn (output) Remark n = 0, 1 User’s Manual U17703EJ2V0UD...
Page 807 CHAPTER 28 ELECTRICAL SPECIFICATIONS C Bus Mode = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV REF0 REF1 = AV = 0 V, C = 50 pF) Parameter...
Page 808 CHAPTER 28 ELECTRICAL SPECIFICATIONS C Bus Mode <113> <114> SCL0 (I/O) <115> <119> <118> <116> <117> <120> <112> <121> <112> SDA0 (I/O) <111> <118> <119> Stop Start Restart Stop condition condition condition condition User’s Manual U17703EJ2V0UD...
Page 809 CHAPTER 28 ELECTRICAL SPECIFICATIONS A/D Converter = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV = BV REF0 REF1 = AV = 0 V) Parameter Symbol...
Page 810 CHAPTER 28 ELECTRICAL SPECIFICATIONS D/A Converter = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV = BV REF0 REF1 = AV = 0 V) Parameter Symbol...
Page 811 CHAPTER 28 ELECTRICAL SPECIFICATIONS Flash Memory Programming Characteristics = −40 to +85°C, V = 2.7 to 5.5 V, 2.7 V ≤ BV ≤ V , 2.7 V ≤ AV ≤ V = EV = AV = EV = BV REF0 REF1 = AV = 0 V, C...
Page 812: Chapter 29 Package Drawings
CHAPTER 29 PACKAGE DRAWINGS 100-PIN PLASTIC QFP (14x20) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.13 mm of 23.2±0.2 its true position (T.P.) at maximum material condition. 20.0±0.2 14.0±0.2 17.2±0.2 0.825 0.575 0.32 +0.08 −0.07 0.13 0.65 (T.P.)
Page 813 CHAPTER 29 PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 16.00±0.20 its true position (T.P.) at maximum material condition. 14.00±0.20 14.00±0.20 16.00±0.20 1.00 1.00 0.22 +0.05 −0.04 0.08...
Page 814: Chapter 30 Recommended Soldering Conditions
Caution Do not use different soldering methods together (except for partial heating). Remarks 1. Products with -A at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended above, please contact an NEC Electronics sales representative.
Page 815: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS <R> The following development tools are available for the development of systems that employ the V850ES/KG2. Figure A-1 shows the development tool configuration. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT compatibles are compatible with PC98-NX series computers.
Page 816 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration Software package Language processing software Debugging software • Integrated debugger • C compiler package • System simulator • Device file Control software • Project manager Embedded software Note 1 • Real-time OS (Windows only) •...
Page 817: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP850 Development tools (software) commonly used with V850 microcontrollers are included Software package for V850 this package. microcontrollers μ Part number: S××××SP850 Remark ×××× in the part number differs depending on the host machine and OS used. μ...
Page 818: Debugging Tools (Hardware)
APPENDIX A DEVELOPMENT TOOLS A.4 Debugging Tools (Hardware) ® A.4.1 When using IECUBE QB-V850ESKX1H The system configuration when connecting the QB-V850ESKX1H to the host machine (PC-9821 series, PC/AT compatible) is shown below. Even if optional products are not prepared, connection is possible. Figure A-2.
Page 819 The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using the V850ES/KG2. It supports integrated debugger ID850QB. This emulator should be used in combination with a power supply unit and emulation probe. Use the USB interface cable to connect this emulator to the host machine.
Page 820: When Using Minicube Qb-V850Mini
(PC-9821 series, PC/AT compatible) is shown below. Even if optional products are not prepared, connection is possible. Figure A-3. System Configuration Using QB-V850ESKX1H-DA (When Using Optional Products) <1> <3> <4> <2> <5> <6> : Optional products <7> <8> <12> V850ES/KG2 <9> <12> <10> <11> Target system User’s Manual U17703EJ2V0UD...
Page 821 MINICUBE. The cable length is approximately 2 m. <4> MINICUBE This on-chip debug emulator serves to debug hardware and software when On-chip debug emulator developing application systems using the V850ES/KG2. It supports integrated debugger ID850QB. <5> OCD cable Cable to connect MINICUBE and the target system.
Page 822: When Using Minicube2 Qb-Mini2
MINICUBE. The cable length is approximately 2 m. <4> MINICUBE2 This on-chip debug emulator serves to debug hardware and software when On-chip debug emulator developing application systems using the V850ES/KG2. It supports integrated debugger ID850QB. <5> 16-pin target cable Cable to connect MINICUBE2 and the target system.
Page 823: Debugging Tools (Software)
APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Software) SM+ for V850ES/Kx2 This simulator is used with V850 microcontrollers. SM+ for V850ES/Kx2 is Windows- System simulator based software. (Under development) Debugging of C source and assembler files is possible during simulation of the target system operation on the host machine.
Page 824: Embedded Software
This file system is used with the real-time OS RX850 Pro. Note For how to obtain Applilet, consult an NEC Electronics sales representative. Caution To purchase the RX850 or RX850 Pro, first fill in the purchase application form and sign the license agreement.
Page 825: Flash Memory Writing Tools
APPENDIX A DEVELOPMENT TOOLS A.7 Flash Memory Writing Tools Flashpro IV Flash programmer dedicated to microcontrollers with on-chip flash memory. (part number: PG-FP4) Flash programmer QB-MINI2 (MINICUBE2) On-chip debug emulator with programming function. FA-100GC-8EU-A Flash memory writing adapter used connected to the Flashpro IV, etc. (not wired). •...
Page 826: Appendix B Instruction Set List
APPENDIX B INSTRUCTION SET LIST B.1 Conventions (1) Register symbols used to describe operands Register Symbol Explanation reg1 General-purpose registers: Used as source registers. reg2 General-purpose registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General-purpose registers: Used mainly to store the remainders of division results and the higher 32 bits of multiplication results.
Page 827 APPENDIX B INSTRUCTION SET LIST (3) Register symbols used in operations Register Symbol Explanation ← Input for GR [ ] General-purpose register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length. load-memory (a, b) Read size b data from address a.
Page 828: Condition Codes
APPENDIX B INSTRUCTION SET LIST (5) Register symbols used in flag operations Identifier Explanation (Blank) No change Clear to 0 Set or cleared in accordance with the results. Previously saved values are restored. (6) Condition codes Condition Code Condition Formula Explanation (cccc) 0 0 0 0...
Page 829: Instruction Set (In Alphabetical Order)
APPENDIX B INSTRUCTION SET LIST B.2 Instruction Set (in Alphabetical Order) (1/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 r r rr r0 01 11 0 RRRRR GR[reg2]←GR[reg2]+GR[reg1] × × ×...
Page 830 APPENDIX B INSTRUCTION SET LIST (2/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT DBTRAP 1111100001000000 DBPC←PC+2 (restored PC) DBPSW←PSW PSW.NP←1 PSW.EP←1 PSW.ID←1 PC←00000060H 0000011111100000 PSW.ID←1 0000000101100000 DISPOSE imm5,list12 0 0 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend(imm5 logically shift left by 2) LLLLLLLLLLL00000 GR[reg in list12]←Load-memory(sp,Word)
Page 831 APPENDIX B INSTRUCTION SET LIST (3/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT LD.H disp16[reg1],reg2 rrrrr111001RRRRR adr←GR[reg1]+sign-extend(disp16) Note ddddddddddddddd0 GR[reg2]←sign-extend(Load-memory(adr,Halfword)) Note 8 LDSR reg2,regID rrrrr111111RRRRR SR[regID]←GR[reg2] Other than regID = PSW 0000000000100000 × × × ×...
Page 832 APPENDIX B INSTRUCTION SET LIST (4/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × reg1,reg2 r r rr r0 01 00 0 RRRRR GR[reg2]←GR[reg2]OR GR[reg1] × × imm16,reg1,reg2 r r rr r1 10 10 0 RRRRR GR[reg2]←GR[reg1]OR zero-extend(imm16) i i i i i i i i i i i i i i i i PREPARE...
Page 833 APPENDIX B INSTRUCTION SET LIST (5/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16) dddddddddddddddd Z flag←Not (Load-memory-bit(adr,bit#3)) Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,1) × reg2,[reg1] r r rr r1 11 11 1 RRRRR adr←GR[reg1] Z flag←Not(Load-memory-bit(adr,reg2)) 0000000011100000...
Page 834 APPENDIX B INSTRUCTION SET LIST (6/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 r r rr r0 01 10 1 RRRRR GR[reg2]←GR[reg2]–GR[reg1] × × × × SUBR reg1,reg2 r r rr r0 01 10 0 RRRRR GR[reg2]←GR[reg1]–GR[reg2] SWITCH reg1 00000000010RRRRR adr←(PC+2) + (GR [reg1] logically shift left by 1)
Page 835 APPENDIX B INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. r r r r r = regID specification RRRRR = reg2 specification...
Page 836: Appendix C Register Index
APPENDIX C REGISTER INDEX (1/9) Symbol Name Unit Page ADCR A/D conversion result register ADCRH A/D conversion result register H ADIC Interrupt control register INTC A/D converter mode register Analog input channel specification register ADTC0 Automatic data transfer address count register 0 CSIA ADTC1 Automatic data transfer address count register 1...
Page 837 APPENDIX C REGISTER INDEX (2/9) Symbol Name Unit Page CR030 16-bit timer capture/compare register 030 CR031 16-bit timer capture/compare register 031 16-bit timer compare register 5 CR50 8-bit timer compare register 50 CR51 8-bit timer compare register 51 CRC00 Capture/compare control register 00 CRC01 Capture/compare control register 01 CRC02...
Page 838 APPENDIX C REGISTER INDEX (3/9) Symbol Name Unit Page DBPSW Exception/debug trap status saving register DCHC0 DMA channel control register 0 DCHC1 DMA channel control register 1 DCHC2 DMA channel control register 2 DCHC3 DMA channel control register 3 DDA0H DMA destination address register 0H DDA0L DMA destination address register 0L...
Page 839 APPENDIX C REGISTER INDEX (4/9) Symbol Name Unit Page IMR0H Interrupt mask register 0H INTC IMR0L Interrupt mask register 0L INTC IMR1 Interrupt mask register 1 INTC IMR1H Interrupt mask register 1H INTC IMR1L Interrupt mask register 1L INTC IMR2 Interrupt mask register 2 INTC IMR2H...
Page 840 APPENDIX C REGISTER INDEX (5/9) Symbol Name Unit Page PF3H Port 3 function register H Port Port 4 function register Port Port 5 function register Port PF9H Port 9 function register H Port PFC3 Port 3 function control register Port PFC4 Port 4 function control register Port...
Page 841 APPENDIX C REGISTER INDEX (6/9) Symbol Name Unit Page PMCDH Port DH mode control register Port PMCDL Port DL mode control register Port PMCDLH Port DL mode control register H Port PMCDLL Port DL mode control register L Port PMCM Port CM mode register Port PMCS...
Page 842 APPENDIX C REGISTER INDEX (7/9) Symbol Name Unit Page SELCNT1 Selector operation control register 1 SIO00 Serial I/O shift register 0 CSI0 SIO00L Serial I/O shift register 0L CSI0 SIO01 Serial I/O shift register 1 CSI0 SIO01L Serial I/O shift register 1L CSI0 SIOA0 Serial I/O shift register A0...
Page 843 APPENDIX C REGISTER INDEX (8/9) Symbol Name Unit Page TM0IC20 Interrupt control register INTC TM0IC21 Interrupt control register INTC TM0IC30 Interrupt control register INTC TM0IC31 Interrupt control register INTC 16-bit timer counter 5 TM50 8-bit timer counter 50 TM51 8-bit timer counter 51 TM5IC0 Interrupt control register INTC...
Page 844 APPENDIX C REGISTER INDEX (9/9) Symbol Name Unit Page WDTM1 Watchdog timer mode register 1 419, 678 WDTM2 Watchdog timer mode register 2 WTIC Interrupt control register INTC WTIIC Interrupt control register INTC Watch timer operation mode register User’s Manual U17703EJ2V0UD...
Page 845: Appendix D List Of Cautions
APPENDIX D LIST OF CAUTIONS <R> This appendix lists cautions described in this document. “Classification (hard/soft)” in table is as follows. Hard: Cautions for microcontroller internal/external hardware Soft: Cautions for software such as register settings or programs (1/39) Function Details of Cautions Page Function...
Page 846 If data is written to the PRCMD register that is not a special register immediately p. 79 following write to the PRCMD register, the PRERR bit becomes 1. Waits on Be sure to set the following registers before using the V850ES/KG2. p. 80 • System wait control register (VSWC) register access •...
Page 847 APPENDIX D LIST OF CAUTIONS (3/39) Function Details of Cautions Page Function PFn register Port The PFnm bit is valid only when the PMn.PMnm bit is 0 (output mode) regardless p. 89 functions of the setting of the PMCn register. When the PMnm bit is 1 (input mode), the set value in the PFn register is invalid.
Page 848 APPENDIX D LIST OF CAUTIONS (4/39) Function Details of Cautions Page Function Port PF9H register When using P98, P99, P911, and P912 as N-ch open-drain-output alternate- p. 114 functions function pins, set in the following sequence. Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output. P9n bit = 1 →...
Page 849 APPENDIX D LIST OF CAUTIONS (5/39) Function Details of Cautions Page Function Pin status when When a write access is performed to the internal ROM area, address, data, and p. 165 control internal ROM, control signals are activated in the same way as access to the external memory functions internal RAM, or area.
Page 850 APPENDIX D LIST OF CAUTIONS (6/39) Function Details of Cautions Page Function Bus control With the external bus function, signals may not be output at the correct timing p. 190 control functions under the following conditions. functions <Operating conditions> Multiplex bus mode CLKOUT asynchronous (2.7 V ≤...
Page 851 APPENDIX D LIST OF CAUTIONS (7/39) Function Details of Cautions Page Function 16-bit TP0CTL1 The TP0EST bit is valid only in the external trigger pulse output mode or one-shot p. 205 timer/ register pulse output mode. In any other mode, writing 1 to this bit is ignored. event External event count input is selected in the external event count mode regardless p.
Page 852 APPENDIX D LIST OF CAUTIONS (8/39) Function Details of Cautions Page Function 16-bit TP0CTL1. This bit can be set to 1 only when the interrupt request signals (INTTP0CC0 and p. 217 timer/ TP0EEE bit INTTP0CC1) are masked by the interrupt mask flags (TP0CCMK0 and event TP0CCMK1) and timer output (TOP01) is performed at the same time.
Page 853 APPENDIX D LIST OF CAUTIONS (9/39) Function Details of Cautions Page Function 16-bit TOC0n register Be sure to set the TOC0n register using the following procedure. p. 298 timer/ <1> Set the TOC0n4 and TOC0n1 bits to 1. event <2> Set only the TOE0n bit to 1. counter 0 <3>...
Page 854 APPENDIX D LIST OF CAUTIONS (10/39) Function Details of Cautions Page Function 16-bit For TM00 To perform the TO00 pin output inversion operation by detecting the valid edge of p. 355 timer/ the TI000 pin input, use the output of the TO00 pin that functions alternately as event P34.
Page 855 APPENDIX D LIST OF CAUTIONS (11/39) Function Details of Cautions Page Function 16-bit Setting CR0n0 Setting CR0n0 and CR0n1 registers (in the mode in which clear & start occurs p. 357 timer/ and CR0n1 upon match between TM0n register and CR0n0 register) event registers Set the CR0n0 and CR0n1 registers to a value other than 0000H (when using...
Page 856 APPENDIX D LIST OF CAUTIONS (12/39) Function Details of Cautions Page Function 16-bit Edge detection For sampling clock for noise elimination, the sampling clock for noise elimination p. 361 timer/ differs depending on whether the valid edge of TI0n0 is used for the count clock event or as a capture trigger.
Page 857 APPENDIX D LIST OF CAUTIONS (13/39) Function Details of Cautions Page Function 8-bit Operation as Do not change the value of the CR5 register during timer operation. p. 377 timer/ interval timer event (16 bits) counter 5 Operation as During external event counter operation, do not rewrite the value of the CR5n p.
Page 858 APPENDIX D LIST OF CAUTIONS (14/39) Function Details of Cautions Page Function 8-bit timer PWM output The set value of the CMPn1 register can be changed while the timer counter is p. 393 mode operation operating. However, this takes a duration of at least three operating clocks (signal selected by the CKSHn2 to CKSHn0 bits of the TMHMDn register) from when the value of the CMPn1 register is changed until the value is transferred to the register.
Page 859 APPENDIX D LIST OF CAUTIONS (15/39) Function Details of Cautions Page Function Interval When interval When using the subclock as the count clock for interval timer WT, the interval p. 415 timer, timer BRG and times of interval timers BRG and WT can be set to any values. They can also be watch interval timer changed later (before changing the value, stop operation).
Page 860 APPENDIX D LIST OF CAUTIONS (16/39) Function Details of Cautions Page Function Watchdog WDTM2 register If the WDTM2 register is written twice after a reset, an overflow signal is forcibly p. 423 timer output. functions To intentionally generate an overflow signal, write data to the WDTM2 register p.
Page 861 APPENDIX D LIST OF CAUTIONS (17/39) Function Details of Cautions Page Function Real-time Conflicts Prevent the following conflicts by software. p. 431 • Conflict between real-time output disable/enable switching (RTPOE0 bit) and output function selected real-time output trigger. • Conflict between write to the RTBH0 and RTBL0 registers in the real-time (RTO) output enabled status and the selected real-time output trigger.
Page 862 APPENDIX D LIST OF CAUTIONS (18/39) Function Details of Cautions Page Function Setting of If the ADCS and ADCS2 bits are changed from 00B to 11B, the reference voltage p. 440 converter ADCS bit and generator for boosting automatically turns on. If the ADCS bit is cleared to 0 while ADCS2 bit the ADCS2 bit is 1, the voltage generator stays on.
Page 863 APPENDIX D LIST OF CAUTIONS (19/39) Function Details of Cautions Page Function Input range of Use the A/D converter with the ANI0 to ANI7 pin input voltages within the p. 452 converter ANI0 to ANI7 specified range. If a voltage of AV or higher or AV or lower (even if within REF0...
Page 864 APPENDIX D LIST OF CAUTIONS (20/39) Function Details of Cautions Page Function Reading A/D When the ADM or ADS register has been written, the contents of the ADCR p. 454 converter conversion register may become undefined. When the conversion operation is complete, result register read the conversion results before writing to the ADM or ADS register.
Page 865 APPENDIX D LIST OF CAUTIONS (21/39) Function Details of Cautions Page Function D/A converter When using the D/A converter, reading of the port is prohibited. p. 466 converter When using the D/A converter, use both P10 and P11 as D/A outputs. p.
Page 866 APPENDIX D LIST OF CAUTIONS (22/39) Function Details of Cautions Page Function Asynchro- TXSFn bit When initializing the transmission unit when continuous transmission is p. 481 nous serial completed, confirm that the TXSFn bit is 0 after the occurrence of the interface transmission completion interrupt, and then execute initialization.
Page 867 APPENDIX D LIST OF CAUTIONS (23/39) Function Details of Cautions Page Function Asynchro- Caution for UARTn has a 2-stage buffer configuration consisting of the TXBn register and the p. 497 nous serial UARTn transmission shift register, and has status flags (ASIFn.TXBFn and ASIFn.TXSFn interface bits) that indicate the status of each buffer.
Page 868 APPENDIX D LIST OF CAUTIONS (24/39) Function Details of Cautions Page Function Clocked Caution for To continue continuous transfers, it is necessary to either read the SIRBn register p. 522 serial continuous or write to the SOTBn register during the transfer reservation period. interface transfer mode In case of conflict between transfer request and register access...
Page 869 APPENDIX D LIST OF CAUTIONS (25/39) Function Details of Cautions Page Function Clocked Automatic Because, in the automatic transmission/reception mode, the automatic p. 543 serial transmission/ transmit/receive function reads/writes data from/to the buffer RAM after 1-byte interface reception mode transmission/reception, an interval is inserted until the next A (CSIA) operation transmission/reception.
Page 870 (IICC0.STT0 bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. IICC0.IICE0 bit When the IICC0.IICE0 bit of the V850ES/KG2 is set to 1 while communications p. 616 is set to 1 with other devices are in progress, the start condition may be detected depending on the status of the communication line.
Page 871 Conform the transmission and reception formats to the specifications of the p. 621 product in communication. When using the V850ES/KG2 as the master in the multimaster system, read the p. 621 IICS0.MSTS0 bit for each INTIIC0 interrupt occurrence to confirm the arbitration result.
Page 872 APPENDIX D LIST OF CAUTIONS (28/39) Function Details of Cautions Page Function DDA0 to DDA3 When the value of the DDAn register is read, two 16-bit registers, DDAnH and p. 635 function registers DDAnL, are read. If reading and updating conflict, a value being updated may be (DMA read (refer to 20.13 Cautions).
Page 873 APPENDIX D LIST OF CAUTIONS (29/39) Function Details of Cautions Page Function Relationship The operation is not guaranteed for combinations of transfer destination and p. 641 function between source marked with “×” in Table 20-2. (DMA transfer targets controller) Request by on- Two start factors (software trigger and hardware trigger) cannot be used for one p.
Page 874 APPENDIX D LIST OF CAUTIONS (30/39) Function Details of Cautions Page Function DMA transfer Even if the INITn bit is set to 1 when the channel executing DMA transfer is to be p. 651 function initialization initialized, the channel may not be initialized. To accurately initialize the channel, (DMA procedure execute either of the following two procedures.
Page 875 APPENDIX D LIST OF CAUTIONS (31/39) Function Details of Cautions Page Function Procedure of Stop and resume the DMA transfer under execution using the following p. 652 function temporarily procedure. (DMA stopping DMA <1> Suppress a transfer request from the DMA request source (stop the controller) transfer operation of the on-chip peripheral I/O).
Page 876 APPENDIX D LIST OF CAUTIONS (32/39) Function Details of Cautions Page Function Read values of Values in the middle of updating may be read from the DSAn and DDAn registers p. 654 function DSAn and during DMA transfer (n = 0 to 3). (DMA DDAn registers For example, if the DSAnH register and then the DSAnL register are read when...
Page 877 APPENDIX D LIST OF CAUTIONS (33/39) Function Details of Cautions Page Function Interrupt/ INTR0 and When switching to the port function from the external interrupt function (alternate p. 682 exception INTF0 registers function), edge detection may be performed. Therefore, set the port mode after process- setting the INTF0n and INTR0n bits = 00.
Page 878 APPENDIX D LIST OF CAUTIONS (34/39) Function Details of Cautions Page Function Standby PSMR register Be sure to clear the XTSTP bit to 0 during subclock resonator connection. p. 702 function Be sure to clear bits 1 to 6 of the PSMR register to 0. p.
Page 879 APPENDIX D LIST OF CAUTIONS (35/39) Function Details of Cautions Page Function Flash Flash memory For the electrical specifications related to the flash memory rewriting, refer to p. 725 memory CHAPTER 28 ELECTRICAL SPECIFICATIONS. PG-FP4 Wire the FLMD1 pin as shown in Figure 26-6, or connect it to GND on board via a p.
Page 880 APPENDIX D LIST OF CAUTIONS (36/39) Function Details of Cautions Page Function Flash Selection of When UART0 is selected, the receive clock is calculated based on the reset p. 740 memory communication command sent from the dedicated flash programmer after receiving the FLMD0 mode pulse.
Page 881 APPENDIX D LIST OF CAUTIONS (37/39) Function Details of Cautions Page Function Electrical Absolute Product quality may suffer if the absolute maximum rating is exceeded even Specifica- maximum momentarily for any parameter. That is, the absolute maximum ratings are rated 765, tions ratings...
Page 882 APPENDIX D LIST OF CAUTIONS (38/39) Function Details of Cautions Page Function μ Electrical Subclock When REGC = 10 F, the supply voltage to the oscillator is the on-chip regulator p. 770 Specifica- oscillator output (3.6 V (TYP.)). However, the supply voltage to the oscillator is V in the tions characteristics...
Page 883 APPENDIX D LIST OF CAUTIONS (39/39) Function Details of Cautions Page Function Electrical Flash memory When writing initially to shipped products, it is counted as one rewrite for both p. 811 Specifica- programming “erase to write” and “write only”. tions characteristics Example (P: Write, E: Erase) Shipped product ⎯⎯→P→E→P→E→P: 3 rewrites...
Page 884: Appendix E Revision History
<R> APPENDIX E REVISION HISTORY E.1 Major Revisions in This Edition Page Description p. 52 Addition of description to 3.2.2 (6) Exception/debug trap status saving registers (DBPC, DBPSW) p. 190 Modification of 5.11 Cautions p. 206 Modification of 7.4 (3) TMP0 I/O control register 0 (TP0IOC0) p.
Page 885 Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [Asia & Oceania] [America] [Europe] NEC Electronics (China) Co., Ltd NEC Electronics America, Inc. NEC Electronics (Europe) GmbH 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian 2880 Scott Blvd. Arcadiastrasse 10 District, Beijing 100083, P.R.China Santa Clara, CA 95050-2554, U.S.A.

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