Processor Common Clock Signal Package Length Compensation; Table 13. Fsb Common Clock Signal Internal Layer Routing Guidelines - Intel 852GM Design Manual

Intel Celeron M Processor Front Side Bus Design Guidelines
to maximize the signal spacing in these areas, it is allowable to have 1:1 trace spacing underneath the
GMCH and the processor package outlines and up to 200 – 300 mils outside the package outline.
Table 13 summarizes the list of common clock and key routing. RESET# (CPURST# of GMCH) is also
a common clock signal but requires a special treatment for the case where an ITP700FLEX debug port is
used. See Section 5.6 for further details.

Table 13. FSB Common Clock Signal Internal Layer Routing Guidelines

Signal Names
CPU
ADS#
BNR#
BPRI#
BR0#
DBSY#
DEFER#
DPWR#
DRDY#
HIT#
HITM#
LOCK#
RS0#
RS1#
RS2#
TRDY#
RESET#
For topologies where an ITP700FLEX debug port is implemented, see Section 5.6 for RESET# (CPURST#)
NOTE:
implementation details.
5.3.1. Processor Common Clock Signal Package Length
Compensation
Trace length matching for the common clock signals is not required. However, package compensation
for the common clock signals is required for the minimum board trace. Please refer to Table 14 and the
example below for more details. Package length compensation should not be confused with length
matching. Length matching refers to constraints on the min and max length bounds of a signal group
based on clock length, whereas package length compensation refers to the process of compensating for
package length variance across a signal group.
All common clock signals are required to meet the minimum pad-to-pad requirement of 2.212 inches,
based on ADS# (as this signal has the longest package lengths). This implies a minimum pin-to-pin
motherboard trace length of 997 mils. Additional motherboard trace will be added to some of the shorter
54
Transmission Line
Type
GMCH
ADS# Strip-line
BNR# Strip-line
BPRI# Strip-line
BR0# Strip-line
DBSY# Strip-line
DEFER# Strip-line
DPWR# Strip-line
DRDY# Strip-line
HIT# Strip-line
HITM# Strip-line
HLOCK# Strip-line
RS0# Strip-line
RS1# Strip-line
RS2# Strip-line
HTRDY# Strip-line
1
CPURST# Strip-line
Total Trace Length
Nominal
Impedance
Min Max
(mils) (inches)
997 6.5 55 ± 15%
1298 6.5 55 ± 15%
1215 6.5 55 ± 15%
1411 6.5 55 ± 15%
1159 6.5 55 ± 15%
1291 6.5 55 ± 15%
1188 6.5 55 ± 15%
1336 6.5 55 ± 15%
1303 6.5 55 ± 15%
1203 6.5 55 ± 15%
1198 6.5 55 ± 15%
1315 6.5 55 ± 15%
1193 6.5 55 ± 15%
1247 6.5 55 ± 15%
1312 6.5 55 ± 15%
1101 6.5 55 ± 15%
®
Intel 852GM Chipset Platform Design Guide
R
Spacing &
Width
(Ω)
2:1
2:1
2:1
2:1
2:1
2:1
2:1
2:1
2:1
2:1
2:1
2:1
2:1
2:1
2:1
2:1