Clock Routing Guidelines; Group Skew And Jitter Limits At The Pins Of The Clock Chip; Signal Group And Resistor - Intel 810A3 Design Manual

6.3

Clock Routing Guidelines

Table 6-2
Table 6-2. Group Skew and Jitter Limits at the Pins of the Clock Chip
Signal Group
CPU
SDRAM
APIC
48 MHz
3V66
PCI
REF
Table 6-3
Table 6-3. Signal Group and Resistor
Signal Group
CPU
SDRAM/DCLK
3V66
PCI
TCLK
OCLK/RCLK
48 MHz
APIC
REF
Table 6-4
Note: All the clock signals must be routed on the same layer which reference to a ground plane.
®
Intel 810A3 Chipset Design Guide
shows the group skew and jitter limits.
Pin-Pin Skew
175 pS
250 pS
250 pS
250 pS
175 pS
500 pS
N/A
shows the Signal Group and Resistor Tolerance.
Resistor
33 Ω ± 5%
22 Ω ± 5%
22 Ω ± 5%
33 Ω ± 5%
22 Ω ± 5%
33 Ω ± 5%
33 Ω ± 5%
33 Ω ± 5%
10 Ω ± 5%
shows the layout dimensions for the clock routing.
Cycle-Cycle Jitter Nominal Vdd
250 pS
250 pS
500 pS
500 pS
500 pS
500 pS
1000 pS
Clocking
Skew, jitter
measure point
2.5V 1.25V
3.3V 1.50V
2.5V 1.25V
3.3V 1.50V
3.3V 1.50V
3.3V 1.50V
3.3V 1.50V
6-3