Routing Guidelines For Common Clock Signals; Wired-Or Signals; Common Clock Signals - Intel Xeon Design Manual

Intel
2.2

Routing Guidelines for Common Clock Signals

Table 6 lists the common clock signals.
Table 6. Common Clock Signals
Signal Type
AGTL+ Common Clock Input
AGTL+ Common Clock I/O
Routing guidelines for the source synchronous signal group are given below:
Trace impedance = 50 Ω ±10%
•
•
Route traces using 5/15 mil spacing
•
Keep signals on the same layer for the entire length of the bus
•
Route traces with at least 50% of the trace width directly over a reference plane
•
Total bus length must not exceed 10"
2.2.1

Wired-OR Signals

There are five wired-OR signals on the system bus. These signals are HIT#, HITM#, MCERR#,
BINIT#, and BNR#. These signals differ from the other front-side bus signals in that more than one
agent can be driving the signal at the same time. Timing and signal integrity must be met for the
case where one agent is driving, all agents are driving, or any combination of agents are driving.
The wired-OR signals should follow the same routing rules as the common clock signals. Intel
recommends that simulations for these signals be performed for a given system.
Platform Design Guide Addendum
®
Xeon™ Processor and Intel
BPRI#
BR[3:1]#
DEFER#
RESET#
RS[2:0]#
RSP#
TRDY#
ADS#
AP[1:0]#
BINIT#
BNR#
BPM[5:0]#
BR0#
DBSY#
DP[3:0]#
DRDY#
HIT#
HITM#
LOCK#
MCERR#
®
E7500/E7501 Chipset Compatible Platform
Signals
13