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7.5.3.2
DDRII 400 Clock Routing Guidelines
This section lists the recommendations for the DDR II 400 Clock signals. Refer to
Table 61
Table 61.
DDRII 400 DIMM Clock Routing Recommendations
Reference Plane
Preferred Topology
Microstrip Trace Width and spacing
Trace Impedance
Trace Spacing
Trace Length 1:80331signal Ball to DIMM connector
Length Matching:
• Within differential clock signals
• With respect to DQ/DQS group (from controller to
DIMM connector)
• With respect to address/command group (from
controller to DIMM connector)
Routing Guideline 1
Routing Guideline 2
Table 62.
DDR II 400 DIMM Clock Lengths
Traces
Description
TL0
Breakout
TL1
Lead-in
Figure 52.
DDR II 400 DIMM Clock Topology
for a description of the segment lengths and matching requirements.
Parameter
Minimum
Maximum
Layer
Length
Microstrip or
0"
0.5"
stripline
Microstrip or
2 "
10"
stripline
Intel® 80331 I/O Processor Design Guide
Unbroken Ground plane
Microstrip differential lines (preferred)
Stripline differential lines
5 mils by 5 mils.
Differential impedance of 100 ohms +/- 15%
Refer to DIMM Clock Topology
> 20 mils between other signals.
2.0"min to 10.0" max correlated within the +/- 1.0" of
the DQ/DQS and command signal length (from 80331
to DIMM connector).
+/- 0.0250" within pairs (intra-pair)
+/- 1.0" maximum
+/- 1.0" maximum
Maximum of 1 via/layer change for differential clocks.
(use the same number of vias between + and - signals
of differential clock)
Route clock signal as differential pair with target
differential impedance of 100 ohms.
Trace
Length
Impedance
Differential
Impedance of
100 ohms
TL0
TL1
Memory Controller
Figure 52
Routing Guideline
Spacing
(edge to
Notes
edge)
5 mils trace width OK for
5 mils
breakout.
Route as differential pair with
target impedance of 100 ohms
Other
correlated within the +/- 1.0" of
groups
the DQ/DQS and command
20 mils
signal length (from 80331 to
DIMM connector).
and
107
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