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ELECTRICAL SPECIFICATIONS
the components. Vcc
account for 19 of the V
termination voltage to the processor and 3 Vcc
TagRAM and BSRAMs. One Vcc
and Vcc
must remain electrically separated from each other. On the circuit board, all
CORE
Vcc
pins must be connected to a voltage island and all Vcc
CORE
a separate voltage island (an island is a portion of a power plane that has been divided, or an
entire plane). Similarly, all V
7.4.
DECOUPLING GUIDELINES
Due to the large number of transistors and high internal clock speeds, the processor is
capable of generating large average current swings between low and full power states. This
causes voltages on power planes to sag below their nominal values if bulk decoupling is not
adequate. Care must be taken in the board design to ensure that the voltage provided to the
processor remains within the specifications listed in this document. Failure to do so can result
in timing violations or a reduced lifetime of the component.
7.4.1.
Pentium
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance
(ESR). This can be accomplished by keeping a maximum distance of 1.5 inches between the
regulator output and Slot 1 connector. The recommended Vcc
wide (the width of the VRM connector) by 1.5 inch long (maximum distance between the
Slot 1 connector and the VRM connector) plane segment with a standard 1-ounce plating.
Please see the Slot 1 Connector Specifications at http://developer.intel.com for more details
on bulk capacitance. Bulk decoupling for the large current swings when the processor is
powering on, or entering/exiting low power states, is provided on the voltage regulation
module (VRM) defined in the Pentium
Vcc
input should be capable of delivering a recommended minimum dIcc
CORE
(defined in Table 7-6) while maintaining the specified tolerances (also defined in Table 7-6).
7.4.2.
System Bus GTL+ Decoupling
The Pentium II processor contains high frequency decoupling capacitance on the processor
substrate; bulk decoupling must be provided for by the system motherboard for proper GTL+
bus operation. See AP-585, Pentium
®
and the Pentium
II Processor Power Distribution Guidelines (Order Number 243332) for
more information.
7-6
inputs for the processor core and some L2 cache components
CORE
pins, while 4 V
CC
pin is provided for use by the debug tools. Vcc
5
pins must be connected to a system ground plane.
SS
®
II Processor Vcc
®
II Processor Power Distribution Guidelines. The
®
II Processor GTL+ Guidelines (Order Number 243330)
inputs (1.5V) are used to provide a GTL+
TT
inputs (3.3V) are for use by the L2 cache
L2
L2
Decoupling
CORE
CORE
, Vcc
5
pins must be connected to
interconnect is a 2.0 inch
CORE
,
L2
/dt
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