Ddr Interface Decoupling Guidelines; 12.5.1.1. Gmch Vccsm Decoupling Guidelines; Figure 102. Ddr Power Delivery Block Diagram - Intel 852GME Design Manual

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Figure 102. DDR Power Delivery Block Diagram

12.5.1.

DDR Interface Decoupling Guidelines

The following decoupling recommendations for the DDR system memory interface are subject to
change.

12.5.1.1. GMCH VCCSM Decoupling Guidelines

Every GMCH ground and VCCSM power ball in the system memory interface should have its own via.
For the VCCSM pins of the GMCH, a minimum of eleven, 0603 form factor, 0.1- , high frequency
capacitors is required and must be placed within 150 mils of the GMCH package. The eleven capacitors
should be evenly distributed along the GMCH DDR system memory interface and must be placed
perpendicular to the GMCH with the power (2.5 V) side of the capacitors facing the GMCH. The trace
from the power end of the capacitor should be as wide as possible and it must connect to a 2.5-V power
ball on the outer row of balls on the GMCH. Each capacitor should have their 2.5-V via placed directly
over and connected to a separate 2.5-V copper finger, and they should be as close to the capacitor pad as
possible, within 25 mils. The ground end of the capacitors must connect to the ground flood and to the
ground plane through a via. This via should be as close to the capacitor pad as possible, within 25 mils,
and with as thick a trace as possible.
® ®
Intel 852GME, Intel 852GMV and Intel
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852PM Chipset Platforms Design Guide
Platform Power Delivery Guidelines
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