Memory Interface Routing Guidelines - Intel Xeon Design Manual

Intel
3.0

Memory Interface Routing Guidelines

This section documents the configurations Intel simulated to support the memory routing
guidelines detailed in the following sections. The customer should simulate any deviations from
these recommendations.
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The Intel
mode. These configurations are defined as follows:
•
Dual channel configuration: The MCH consist of two DDR memory channels, channels A and
B, that operate in 'lock-step'. Each channel consists of 64 data and eight ECC bits. Logically,
this is one, 144-bit wide memory bus; however, each channel is separate electrically. Intel
E7500 supports only dual channel.
•
Single channel configuration: The MCH consists of one DDR memory channel, channel A.
The channel consists of 64 data and 8 ECC bits.
To differentiate between dual and single channel requirements this section is divided into two
subsections:
•
Section 3.2, "Dual Channel DDR Overview"
configuration.
•
Section 3.3, "Single Channel DDR Overview"
configuration.
Each section covers its associated routing guidelines for the memory interface. Note that these
guidelines apply to channel A and channel B for dual channel operation or channel A for single
channel operation.
Refer to the Intel
251927) for details on the signals.
Platform Design Guide Addendum
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Xeon™ Processor and Intel
E7501 chipset may operate in a dual or single DDR channel configuration in DDR200
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E7501 Chipset Memory Controller Hub (MCH) Datasheet (order number
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E7500/E7501 Chipset Compatible Platform
describes the requirements for a dual channel
describes the requirements for a single channel
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