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2.2
Power and Ground Lands
For clean on-chip processor core power distribution, the processor has 223 V
and 267 V
plane, while all V
processor V
Voltage IDentification (VID) signals. See
Twenty two lands are specified as V
provides power to the I/O buffers. The platform must implement a separate supply for
these lands which meets the V
2.3
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large average current swings between low and full power states.
This may cause voltages on power planes to sag below their minimum values if bulk
decoupling is not adequate. Larger bulk storage (C
supply current during longer lasting changes in current demand by the component,
such as coming out of an idle condition. Similarly, they act as a storage well for current
when entering an idle condition from a running condition. Care must be taken in the
baseboard design to ensure that the voltage provided to the processor remains within
the specifications listed in
reduced lifetime of the component. For further information and guidelines, refer to the
appropriate platform design guidelines.
2.3.1
V
Decoupling
CC
Vcc regulator solutions need to provide bulk capacitance with a low Effective Series
Resistance (ESR), and the baseboard designer must assure a low interconnect
resistance from the regulator (EVRD or VRM pins) to the LGA771 socket. Bulk
decoupling must be provided on the baseboard to handle large current swings. The
power delivery solution must insure the voltage and current specifications are met (as
defined in
and layout guidelines, refer to the appropriate platform design guidelines.
2.3.2
V
Decoupling
TT
Bulk decoupling must be provided on the baseboard. Decoupling solutions must be
sized to meet the expected load. To insure optimal performance, various factors
associated with the power delivery solution must be considered including regulator
type, power plane and trace sizing, and component placement. A conservative
decoupling solution consists of a combination of low ESR bulk capacitors and high
frequency ceramic capacitors. For further information regarding power delivery,
decoupling and layout guidelines, refer to the appropriate platform design guidelines.
18
(ground) inputs. All V
SS
lands must be connected to the system ground plane. The
SS
lands must be supplied with the voltage determined by the processor
CC
specifications outlined in
TT
Table
2-12. Failure to do so can result in timing violations or
Table
2-12). For further information regarding power delivery, decoupling
lands must be connected to the processor power
CC
Table 2-3
for VID definitions.
, which provide termination for the FSB and
TT
), such as electrolytic capacitors,
BULK
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Electrical Specifications
(power)
CC
Table
2-12.
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