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•
For high-speed signals, the number of corners and vias should be kept to a minimum. When a
90 degree bend is required, it is recommended to use two 45-degree bends instead. Refer to
Figure
•
Traces should be routed away from board edges by a distance greater than the trace height
above the ground plane. This allows the field around the trace to couple more easily to the
ground plane rather than to adjacent wires or boards.
•
Do not route traces and vias under crystals or oscillators. This may prevent coupling to or from
the clock. And as a general rule, place traces from clocks and drives at a minimum distance
from apertures by a distance that is greater than the largest aperture dimension.
Figure 120.
Routing a 90-Degree Bend
9.7.2.2
Trace Geometry and Length
The key factors in controlling trace EMI radiation are the trace length, and the ratio of trace-width
to trace-height above the ground plane. To minimize trace inductance, high-speed signals and
signal layers that are close to a ground or power plane should be as short and wide as practical.
Ideally, this trace width to height above the ground plane ratio is between 1:1 and 3:1. To maintain
trace impedance, the width of the trace should be modified when changing from one board layer to
another when the two layers are not equidistant from the power or ground plane. Differential trace
impedances should be controlled to be ~100 Ω. It is necessary to compensate for trace-to-trace edge
coupling, which may lower the differential impedance by up to 10 Ω.
Traces between decoupling and I/O filter capacitors should be as short and wide as practical. Long
and thin traces are more inductive and would reduce the intended effect of decoupling capacitors.
Also, for similar reasons, traces to I/O signals and signal terminations should be as short as
possible. Vias to the decoupling capacitors should be sufficiently large in diameter to decrease
series inductance. Additionally, the PLC should not be closer than 1 inch to the connector/magnetic
edge of the board.
9.7.2.3
Signal Isolation
Follow these rules for signal isolation:
•
Separate and group signals by function on separate layers when possible. Maintain a gap of
100 mils between all differential pairs (Ethernet) and other nets, but group associated
differential pairs together. Over the length of the trace run, each differential pair should be at
least 0.3 inch away from any parallel signal traces.
Design Guide
®
Intel
Pentium
120.
45°
®
M Processor and Intel
I/O Controller Hub 3 (Intel
®
E7501 Chipset Platform
®
ICH3-S)
171
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