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• Keep the total length of each differential pair under 4 inches. (Many customer designs with
differential traces longer than 5 inches have had one or more of the following issues: IEEE phy
conformance failures, excessive EMI (Electro Magnetic Interference), and/or degraded receive
BER (Bit Error Rate).)
• Do not route the transmit differential traces closer than 100 mils to the receive differential traces.
• Do not route any other signal traces both parallel to the differential traces, and closer than 100 mils
to the differential traces (300 mils is recommended).
• Keep maximum separation between differential pairs to 7 mils.
• For high-speed signals, the number of corners and vias should be kept to a minimum. If a 90° bend
is required, it is recommended to use two 45° bends instead. Refer to Figure 102.
• Traces should be routed away from board edges by a distance greater than the trace height above
the ground plane. This allows the field around the trace to couple more easily to the ground plane
rather than to adjacent wires or boards.
• Do not route traces and vias under crystals or oscillators. This will prevent coupling to or from the
clock. And as a general rule, place traces from clocks and drives at a minimum distance from
apertures by a distance that is greater than the largest aperture dimension.
Figure 102. Trace Routing
10.9.4.1.1. Trace Geometry and Length
The key factors in controlling trace EMI radiation are the trace length and the ratio of trace-width to
trace-height above the ground plane. To minimize trace inductance, high-speed signals and signal layers
that are close to a ground or power plane should be as short and wide as practical. Ideally, this trace
width to height above the ground plane ratio is between 1:1 and 3:1. To maintain trace impedance, the
width of the trace should be modified when changing from one board layer to another if the two layers
are not equidistant from the power or ground plane. Differential trace impedances should be controlled
to be ~100 Ω . It is necessary to compensate for trace-to-trace edge coupling, which can lower the
differential impedance by up to 10 Ω , when the traces within a pair are closer than 30 mils (edge to
edge).
Traces between decoupling and I/O filter capacitors should be as short and wide as practical. Long and
thin traces are more inductive and would reduce the intended effect of decoupling capacitors. Also for
similar reasons, traces to I/O signals and signal terminations should be as short as possible. Vias to the
®
Intel
852GM Chipset Platform Design Guide
45
I/O Subsystem
Trace Routing
189
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