Maximum Trace Lengths Based On Trace Geometry And Board Stack-Up - Intel Quark SoC X1000 Design Manual

LAN Design Considerations and Guidelines—Intel
provided to allow for board manufacturing process variations and not lower target impedances. The
minimum value of impedance cannot be lower than 85.
3. Simulation shows 80 differential trace impedances degrade MDI return loss measurements by
approximately 1 dB from that of 90.
4. Stripline is NOT recommended due to thinner more resistive signal layers.
5. Use a minimum of 21 mil (0.533 mm) pair-to-pair spacing for board designs that use the CRB design
stack-up. Using dielectrics that are thicker than the CRB stack-up might require larger pair-to-pair
spacing.
6. For applications that require a longer MDI trace length of more than 8 inches (20.32 mm), it is
recommended that thicker dielectric or lower Er materials be used. This permits higher differential trace
impedance and wider, lower loss traces. Refer to
for common circuit board materials.
7. Intel® Quark™ SoC designs without LAN switch can range up to ~8 inches. Refer to
length information.
Table 69.

Maximum Trace Lengths Based on Trace Geometry and Board Stack-Up

Dielectric
Thickness
(mils)
2.7
2.7
2.7
3.3
3.3
3.3
4
4
4
Notes:
1. Longer MDI trace lengths may be achievable, but may make it more difficult to achieve IEEE
conformance. Simulations have shown deviations are possible if traces are kept short. Longer traces are
possible; use cost considerations and stack-up tolerance for differential pairs to determine length
requirements.
2. Deviations from 100? nominal and/or tolerances greater than 15% decrease the maximum length for
IEEE conformance.
Note: Use the MDI Differential Trace Calculator to determine the maximum MDI trace length
for your trace geometry and board stack-up. Contact your Intel representative for
access.
The following factors can limit the maximum MDI differential trace lengths for IEEE
conformance:
• Dielectric thickness
• Dielectric constant
• Nominal differential trace impedance
• Trace impedance tolerance
• Copper trace losses
• Additional devices, such as switches, in the MDI path may impact IEEE
conformance
Board geometry should also be factored in when setting trace length.
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
Dielectric Width /
Constant Space/
Pair Space
(DK) at Width
1 MHz (mils)
4.05 4/10/4
4.05 4/10/4
4.05 4/10/4
4.1 4.2/9/4.2
4.1 4.2/9/4.2
4.1 4.2/9/4.2
4.2 5/9/5
4.2 5/9/5
4.2 5/9/5
Table 69 for examples of microstrip trace geometries
Pair-to- Nominal
Impedance
(mils) (Ohms)
2
19 95
2
19 95
19 95
2
23 100
23 100
23 100
2
28 100
28 100
28 100
Table 69 for trace
Impedance Maximum
Tolerance Trace Length
1
(±%) (inches)
2
17 3.5
2
15 4
10 5
2
17 4
15 4.6
10 6
2
17 4.5
15 5.3
10 7
®
Intel Quark™ SoC X1000
PDG
155