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Px Port Interrupt Flag Register
Register name
Bit
PPORTPxINTF
15–8
7–0
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8
Reserved
Bits 7–0
PxIF[7:0]
These bits indicate the port input interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
Px Port Interrupt Control Register
Register name
Bit
PPORTPxINTCTL
15–8
7–0
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8
PxEDGE[7:0]
These bits select the input signal edge to generate a port input interrupt.
1 (R/W): An interrupt will occur at a falling edge.
0 (R/W): An interrupt will occur at a rising edge.
Bits 7–0
PxIE[7:0]
These bits enable port input interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Note:
To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared
before enabling interrupts.
Px Port Chattering Filter Enable Register
Register name
Bit
PPORTPxCHATEN
15–8
7–0
*1: The bit configuration differs depending on the port group.
Bits 15–8
Reserved
Bits 7–0
PxCHATEN[7:0]
These bits enable/disable the chattering filter function.
1 (R/W): Enable (The chattering filter is used.)
0 (R/W): Disable (The chattering filter is bypassed.)
7-10
Bit name
Initial
–
0x00
PxIF[7:0]
0x00
Bit name
Initial
PxEDGE[7:0]
0x00
PxIE[7:0]
0x00
Bit name
Initial
–
0x00
PxCHATEN[7:0]
0x00
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/W
Cleared by writing 1.
Reset
R/W
H0
R/W
H0
R/W
Reset
R/W
–
R
H0
R/W
Remarks
–
Remarks
–
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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