Advertisement
13.6. Receive Errors
Three different receive errors, framing error, parity error, and overrun error, may be detected while
receiving data. Since receive errors are interrupt causes, they can be processed by generating interrupts.
13.6.1. Framing Error
The UART3 determines loss of sync if a stop bit is not detected (when the stop bit is received as 0) and
assumes that a framing error has occurred. The received data that encountered an error is still
transferred to the receive data buffer and the UART3_nINTF.FEIF bit (framing error interrupt flag) is set
to 1 when the data becomes ready to read from the UART3_nRXD register.
Note:
Framing error/parity error interrupt flag set timings
These interrupt flags will be set after the data that encountered an error is transferred to the re-
ceive data buffer. Note, however, that the set timing depends on the buffer status at that point.
When the receive data buffer is empty
•
The interrupt flag will be set when the data that encountered an error is transferred to the
receive data buffer.
When the receive data buffer has a one-byte free space
•
The interrupt flag will be set when the first data byte already loaded is read out after the
data that encountered an error is transferred to the second byte entry of the receive data
buffer.
13.6.2. Parity Error
If the parity function is enabled, a parity check is performed when data is received. The UART3 checks
matching between the data received in the shift register and its parity bit, and issues a parity error if the
result is a non-match. The received data that encountered an error is still transferred to the receive
data buffer and the UART3_nINTF. PEIF bit (parity error interrupt flag) is set to 1 when the data becomes
ready to read from the UART3_nRXD register (see the Note on framing error).
13.6.3. Overrun Error
If the receive data buffer is still full (two bytes of received data have not been read) when a data
reception to the shift register has completed, an overrun error occurs as the data cannot be transferred
to the receive data buffer. When an overrun error occurs, the UART3_nINTF.OEIF bit (overrun error
interrupt flag) is set to 1.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Seiko Epson Corporation
13-11
Advertisement
