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Epson S1C31D50 Technical Instructions page 425

Cmos 32-bit single chip microcontroller
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0x0020 0690–0x0020 06a8
Address
Register name
QSPI_0MOD
0x0020
(QSPI Ch.0 Mode
0690
Register)
QSPI_0CTL
0x0020
(QSPI Ch.0 Control
0692
Register)
QSPI_0TXD
0x0020
(QSPI Ch.0
0694
Transmit Data
Register)
QSPI_0RXD
0x0020
(QSPI Ch.0
0696
Receive Data
Register)
QSPI_0INTF
0x0020
(QSPI Ch.0
0698
Interrupt Flag
Register)
QSPI_0INTE
0x0020
(QSPI Ch.0
069a
Interrupt Enable
Register)
QSPI_0TBEDMAEN
(QSPI Ch.0
0x0020
Transmit Buffer
069c
Empty DMA
Request Enable
Register)
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Quad Synchronous Serial Interface (QSPI) Ch.0
Bit
15–12
CHDL[3:0]
11–8
CHLN[3:0]
7–6
TMOD[1:0]
5
PUEN
4
NOCLKDIV
3
LSBFST
2
CPHA
1
CPOL
0
MST
15–8
7–4
3
DIR
2
MSTSSO
1
SFTRST
0
MODEN
15–0
TXD[15:0]
15–0
RXD[15:0]
15–8
7
BSY
6
MMABSY
5–4
3
OEIF
2
TENDIF
1
RBFIF
0
TBEIF
15–8
7–4
3
OEIE
2
TENDIE
1
RBFIE
0
TBEIE
15–8
7–4
3–0
TBEDMAEN[3:0]
Seiko Epson Corporation
Bit name
Initial
Reset
0x7
0x7
0x0
0
0
0
0
0
0
0x00
0x0
0
1
0
0
0x0000
0x0000
0x00
0
0
0x0
0
H0/S0
0
H0/S0
0
H0/S0
1
H0/S0
0x00
0x0
0
0
0
0
0x00
0x0
0x0
R/W
Remarks
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
R
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R
R
H0
R
H0
R
R
R/W
Cleared by
writing 1.
R/W
Cleared by
reading the
R
QSPI_0RXD
register.
Cleared by
writing to the
R
QSPI_0TXD
register.
R
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
R
R
H0
R/W
B-47

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