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Epson S1C17M20 Technical Manual

Cmos 16-bit single chip microcontroller.
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CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17M20/M21/M22/M23/M24/M25
Technical Manual
Rev. 1.0

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   Summary of Contents for Epson S1C17M20

  • Page 1

    CMOS 16-BIT SINGLE CHIP MICROCONTROLLER S1C17M20/M21/M22/M23/M24/M25 Technical Manual Rev. 1.0...

  • Page 2

    No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability...

  • Page 3

    PREFACE Preface This is a technical manual for designers and programmers who develop a product using the S1C17M20/M21/ M22/M23/M24/M25. This document describes the functions of the IC, embedded peripheral circuit operations, and their control methods. For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions and operations of the debugging tools, refer to the respective tool manuals.

  • Page 4: Table Of Contents

    1 Overview ........................1-1 1.1 Features .......................... 1-1 1.2 Block Diagram ......................... 1-3 1.3 Pins ..........................1-4 1.3.1 S1C17M20/M23 Pin Configuration Diagram ............ 1-4 1.3.2 S1C17M21/M24 Pin Configuration Diagram ............ 1-6 1.3.3 S1C17M22/M25 Pin Configuration Diagram ............ 1-7 1.3.4 Pin Descriptions ....................1-8 2 Power Supply, Reset, and Clocks ................2-1...

  • Page 5: Table Of Contents

    6.3.2 Clock Supply in SLEEP Mode ................6-4 6.3.3 Clock Supply in DEBUG Mode ................. 6-4 6.4 Operations ........................6-4 6.4.1 Initialization ....................... 6-4 6.4.2 Port Input/Output Control ................. 6-5 6.5 Interrupts ......................... 6-6 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 6: Table Of Contents

    9.4.2 Real-Time Clock Counter Operations ............... 9-4 9.4.3 Stopwatch Control .................... 9-4 9.4.4 Stopwatch Count-up Pattern ................9-4 9.5 Interrupts ......................... 9-5 9.6 Control Registers ......................9-6 RTC Control Register ........................ 9-6 RTC Second Alarm Register ..................... 9-7 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 7: Table Of Contents

    T16 Ch.n Control Register ......................11-5 T16 Ch.n Reload Data Register ....................11-6 T16 Ch.n Counter Data Register ....................11-6 T16 Ch.n Interrupt Flag Register ....................11-6 T16 Ch.n Interrupt Enable Register ..................11-7 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 8: Table Of Contents

    13.5 Operations ........................13-5 13.5.1 Initialization ....................13-5 13.5.2 Data Transmission in Master Mode ............... 13-5 13.5.3 Data Reception in Master Mode ..............13-7 13.5.4 Terminating Data Transfer in Master Mode ............ 13-8 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 9: Table Of Contents

    15.3.4 Event Counter Clock ..................15-3 15.4 Operations ........................15-4 15.4.1 Initialization ....................15-4 15.4.2 Counter Block Operations ................15-5 15.4.3 Comparator/Capture Block Operations ............15-8 15.4.4 TOUT Output Control ................... 15-16 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 10: Table Of Contents

    17.4.4 Continuous Data Transmission and Compare Buffers........17-5 17.5 Interrupts ........................17-6 17.6 Application Example: Driving EL Lamp ................ 17-7 17.7 Control Registers ......................17-7 REMC3 Clock Control Register ....................17-7 Seiko Epson Corporation viii S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 11: Table Of Contents

    ADC12A Ch.n Trigger/Analog Input Select Register ..............19-7 ADC12A Ch.n Configuration Register ..................19-8 ADC12A Ch.n Interrupt Flag Register ..................19-9 ADC12A Ch.n Interrupt Enable Register ................. 19-10 ADC12A Ch.n Result Register m ..................... 19-10 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 12

    Sound Generator (SNDA) ............AP-A-27 0x5320–0x5332 IR Remote Controller (REMC3) ..........AP-A-28 0x5440–0x5450 R/F Converter (RFC) Ch.0 (S1C17M22/M25) ......AP-A-29 0x5460–0x5470 R/F Converter (RFC) Ch.1 (S1C17M22/M25) ......AP-A-30 0x5480–0x548c 16-bit Timer (T16) Ch.3 ............AP-A-31 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 13: Table Of Contents

    B.1 Operating Status Configuration Examples for Power Saving ........AP-B-1 B.2 Other Power Saving Methods ..................AP-B-2 Appendix C Mounting Precautions ................AP-C-1 Appendix D Measures Against Noise ................ AP-D-1 Appendix E Initialization Routine ................AP-E-1 Revision History Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 14: Overview

    1 OVERVIEW 1 Overview The S1C17M20/M21/M22/M23/M24/M25 is a 16-bit embedded Flash MCU that features low power consump- tion. The embedded Flash memory can also be used as an EEPROM emulation data memory via software. The S1C17M20/M21/M22/M23/M24/M25 includes various serial interfaces, an A/D converter, and various timers as well as a high-performance 16-bit CPU.

  • Page 15: Multiplier/divider (copro2)

    OSC3 = 1 MHz (ceramic oscillator), OSC1 = 32.768 kHz (crystal oscillator), RTC = ON, CPU = OSC3 Shipping form Package SQFN4-24 SQFN5-32 TQFP12-32pin TQFP12-48pin (Lead pitch) (0.5 mm) (0.5 mm) (0.8 mm) (0.5 mm) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 16: Block Diagram

    16-bit PWM timer CAP00–01 (T16B) CAP10–11 2Ch. EXCL00–01 EXCL10–11 * The pin configuration and peripheral circuit function depends on the model. For detailed information, refer to Section 1.3, “Pins.” Figure 1.2.1 S1C17M20/M21/M22/M23/M24/M25 Block Diagram Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 17: Pins

    1.3.1 S1C17M20/M23 Pin Configuration Diagram SQFN4-24 Port function or signal assignment name P01/EXCL01/UPMUX P02/BZOUT/UPMUX S1C17M20 P32/RTC1S/UPMUX/EXSVD0 P03/#BZOUT/UPMUX S1C17M23 P31/EXOSC/UPMUX P12/REMO/UPMUX P30/UPMUX/VREFA0 (Top View) P13/FOUT/UPMUX P27/UPMUX/ADIN00 Figure 1.3.1.1 S1C17M20/M23 Pin Configuration Diagram (SQFN4-24) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 18

    Port function or signal name assignment P01/EXCL01/UPMUX P02/BZOUT/UPMUX OSC2 OSC2 P03/#BZOUT/UPMUX S1C17M20 OSC1 OSC1 P10/UPMUX S1C17M23 P32/RTC1S/UPMUX/EXSVD0 P11/UPMUX P31/EXOSC/UPMUX (Top View) P12/REMO/UPMUX P30/UPMUX/VREFA0 P13/FOUT/UPMUX P27/UPMUX/ADIN00 Figure 1.3.1.2 S1C17M20/M23 Pin Configuration Diagram (SQFN5-32) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 19: S1c17m21/m24 Pin Configuration Diagram

    TQFP12-32pin Port function or signal assignment Pin name P01/EXCL01/UPMUX P02/BZOUT/UPMUX P03/#BZOUT/UPMUX OSC2 OSC2 S1C17M21 P10/UPMUX OSC1 OSC1 S1C17M24 P11/UPMUX P32/RTC1S/UPMUX/EXSVD0 P31/EXOSC/UPMUX P12/REMO/UPMUX P30/UPMUX/VREFA0 P13/FOUT/UPMUX P27/UPMUX/ADIN00 Figure 1.3.2.1 S1C17M21/M24 Pin Configuration Diagram (TQFP12-32pin) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 20: S1c17m22/m25 Pin Configuration Diagram

    P01/EXCL01/UPMUX P02/BZOUT/UPMUX OSC2 OSC2 P03/#BZOUT/UPMUX OSC1 OSC1 P10/UPMUX P04/RFCLKO0/UPMUX P36/RFIN0/UPMUX S1C17M22 P05/RFCLKO1/UPMUX P35/REF0/UPMUX S1C17M25 P06/UPMUX P34/SENA0/UPMUX P07/UPMUX P33/SENB0/UPMUX P32/RTC1S/UPMUX/EXSVD0 P11/UPMUX P31/EXOSC/UPMUX P12/REMO/UPMUX P30/UPMUX/VREFA0 P13/FOUT/UPMUX P27/UPMUX/ADIN00 Figure 1.3.3.1 S1C17M22/M25 Pin Configuration Diagram (TQFP12-48pin) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 21: Pin Descriptions

    User-selected I/O (universal port multiplexer) – ✓ ✓ Hi-Z I/O port ✓ ✓ ✓ ✓ REMO IR remote controller transmit data output ✓ ✓ ✓ UPMUX User-selected I/O (universal port multiplexer) ✓ ✓ ✓ Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 22

    User-selected I/O (universal port multiplexer) – – ✓ Hi-Z I/O port – – ✓ ✓ REF0 R/F converter Ch.0 reference oscillator pin – – ✓ UPMUX User-selected I/O (universal port multiplexer) – – ✓ Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 23

    = 0, 1 16-bit PWM timer (T16B) TOUTn0/CAPn0 T16B Ch.n PWM output/capture input 0 TOUTn1/CAPn1 T16B Ch.n PWM output/capture input 1 Note: Do not assign a function to two or more pins simultaneously. Seiko Epson Corporation 1-10 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 24: Power Supply, Reset, And Clocks

    Use the V regulator in automatic mode when no special control is required. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 25: System Reset Controller (src)

    #RESET pin, so the pin can be left open. For the #RESET pin characteris- tics, refer to “#RESET pin characteristics” in the “Electrical Characteristics” chapter. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 26: Reset Sources

    Table 2.2.4.1 lists the reset groups. For the reset group to initialize the registers and con- trol bits, refer to the “CPU and Debugger” chapter or “Control Registers” in each peripheral circuit chapter. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25...

  • Page 27: Clock Generator (clg)

    - The oscillator and clock input circuit on/off state can be maintained or changed at SLEEP mode cancelation. • Provides the FOUT function to output an internal clock for driving external ICs or for monitoring the internal state. Figure 2.3.1.1 shows the CLG configuration. Table 2.3.1.1 CLG Configuration of S1C17M20/M21/M22/M23/M24/M25 S1C17M20/M23 Item...

  • Page 28: Input/output Pins

    2.3.3 Clock Sources IOSC oscillator circuit The IOSC oscillator circuit features a fast startup and no external parts are required for oscillating. Figure 2.3.3.1 shows the configuration of the IOSC oscillator circuit. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 29

    Figure 2.3.3.2 OSC1 Oscillator Circuit Configuration For the recommended parts and the oscillation characteristics, refer to the “Basic External Connection Dia- gram” chapter and “OSC1 oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respec- tively. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 30

    EXOSC has no oscillation stabilization waiting circuit included, therefore, it must be enabled when a stabilized clock is being supplied. For the input clock characteristics, refer to “EXOSC external clock input characteris- tics” in the “Electrical Characteristics” chapter. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 31: Operations

    Figure 2.3.4.2 shows an operation example when the oscillation startup control circuit is used. (1) CLGOSC1.OSC1BUP bit = 0 (startup boosting operation disabled) Oscillator circuit enable (CLGOSC.OSC1EN) Oscillation inverter INV1N[1:0] setting gain Oscillation waveform Normal operation Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 32

    In addition to the above, configure the following bits when using the crystal/ceramic oscillator: - CLGOSC3.OSC3INV[1:0] bits (Set oscillation inverter gain) Configure the following bits when using the internal oscillator: - CLGOSC3.OSC3FQ[1:0] bits (Select oscillation frequency) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 33

    This allows flexible clock control according to the wake-up process. Configure the clock using the CLGSCLK.WUPSRC[1:0] and CLGSCLK.WUPDIV[1:0] bits, and write 1 to the CLGSCLK.WUPMD bit to enable this function. Seiko Epson Corporation 2-10 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 34

    10 ms is required. When OSC3CLK is be- ing used as the system clock or a peripheral circuit clock, do not use the auto-trimming function. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 2-11 TECHNICAL MANUAL (Rev.

  • Page 35: Operating Mode

    RUN mode. HALT mode is classified into “IOSC HALT,” “OSC1 HALT,” “OSC3 HALT,” and “EXOSC HALT” by the SYSCLK clock source. Seiko Epson Corporation 2-12 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 36

    CLGSCLK.CLKSRC[1:0] = 0x3 EXOSC HALT OSC3 OSC3 ∗ In RUN and HALT modes, the clock sources not used HALT as SYSCLK can be all disabled. Figure 2.4.2.1 Operating Mode-to-Mode State Transition Diagram Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 2-13 TECHNICAL MANUAL (Rev. 1.0)

  • Page 37: Interrupts

    Bits 15–2 Reserved Bits 1–0 REGMODE[1:0] These bits control the internal regulator operating mode. Table 2.6.1 Internal Regulator Operating Mode PWGVD1CTL.REGMODE[1:0] bits Operating mode Economy mode Normal mode Reserved Automatic mode Seiko Epson Corporation 2-14 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 38: Clg System Clock Control Register

    These bits set the division ratio of the clock source to determine the SYSCLK frequency. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the SYSCLK clock source. When a currently stopped clock source is selected, it will automatically start oscillating or clock input. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 2-15 TECHNICAL MANUAL (Rev. 1.0)

  • Page 39: Clg Oscillation Control Register

    Stop oscillating or clock input Each bit corresponds to the clock source as follows: CLGOSC.EXOSCEN bit: EXOSC clock input CLGOSC.OSC3EN bit: OSC3 oscillator circuit CLGOSC.OSC1EN bit: OSC1 oscillator circuit CLGOSC.IOSCEN bit: IOSC oscillator circuit Seiko Epson Corporation 2-16 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 40: Clg Osc1 Control Register

    ” in the “Electrical Characteristics” chapter. GI1C Bits 7–6 INV1B[1:0] These bits set the oscillation inverter gain that will be applied at boost startup of the OSC1 crystal os- cillator circuit. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 2-17 TECHNICAL MANUAL (Rev. 1.0)

  • Page 41: Clg Osc3 Control Register

    20 MHz 16 MHz 12 MHz Bit 9 OSC3MD This bit selects an oscillator type of the OSC3 oscillator circuit. 1 (R/WP): Crystal/ceramic oscillator 0 (R/WP): Internal oscillator Bits 8–6 Reserved Seiko Epson Corporation 2-18 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 42: Clg Interrupt Flag Register

    Reset Remarks CLGINTF 15–8 – 0x00 – – – – (reserved) OSC1STPIF Cleared by writing 1. OSC3TEDIF – – – OSC3STAIF Cleared by writing 1. OSC1STAIF IOSCSTAIF Bits 15–6, 3 Reserved Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 2-19 TECHNICAL MANUAL (Rev. 1.0)

  • Page 43: Clg Interrupt Enable Register

    CLGINTE.OSC3TEDIE bit: OSC3 oscillation auto-trimming completion interrupt CLGINTE.OSC3STAIE bit: OSC3 oscillation stabilization waiting completion interrupt CLGINTE.OSC1STAIE bit: OSC1 oscillation stabilization waiting completion interrupt CLGINTE.IOSCSTAIE bit: IOSC oscillation stabilization waiting completion interrupt Seiko Epson Corporation 2-20 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 44: Clg Fout Control Register

    0 (R/W): Disable external output Note: Since the FOUT signal generated is out of sync with writings to the CLGFOUT.FOUTEN bit, a glitch may occur when the FOUT output is enabled or disabled. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 2-21 TECHNICAL MANUAL (Rev. 1.0)

  • Page 45: Cpu And Debugger

    3 CPU AND DEBUGGER 3 CPU and Debugger 3.1 Overview This IC incorporates the Seiko Epson original 16-bit CPU core (S1C17) with a debugger. The main features of the CPU core are listed below. • Seiko Epson original 16-bit RISC processor...

  • Page 46: Cpu Core

    Debugging requires a 64-byte debugging work area. For more information on the work area location, refer to the “Memory and Bus” chapter. The start address of this debugging work area can be read from the DBRAM register. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 47: List Of Debugger Input/output Pins

    ROM data and password are recorded. file.PA ROM data and password process Mask data file IC with protected Flash Shipment Figure 3.3.5.1 Shipment of IC with ROM Data Programmed and Flash Security Function Setting Flow Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 48: Control Register

    – 23–0 DBRAM[23:0] *1 Debugging work area start address Bits 31–24 Reserved Bits 23–0 DBRAM[23:0] The start address of the debugging work area (64 bytes) can be read out with these bits. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 49: Memory And Bus

    Access size designated by the CPU instructions (e.g., ld %rd, [%rb] → 16-bit data transfer) • Access size: Table 4.2.1 lists numbers of bus access cycles by different device size and access size. The peripheral circuits can be accessed with an 8-bit, 16-bit, or 32-bit instruction. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 50: Flash Memory

    The number of bus access cycles for reading can be configured using the FLASHCWAIT.RDWAIT[1:0] bits. Select a setting for higher frequency than the system clock. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 51: Flash Programming

    The control registers for the peripheral circuits are located in the 8K-byte area beginning with address 0x4000. Table 4.5.1 shows the control register map. For details of each control register, refer to “List of Peripheral Circuit Registers” in the appendix or “Control Registers” in each peripheral circuit chapter. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 52

    0x420c P0MODSEL P0 Port Mode Select Register 0x420e P0FNCSEL P0 Port Function Select Register 0x4210 P1DAT P1 Port Data Register 0x4212 P1IOEN P1 Port Enable Register 0x4214 P1RCTL P1 Port Pull-up/down Control Register Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 53

    UART3 Ch.0 Transmit Data Register 0x438a UA0RXD UART3 Ch.0 Receive Data Register 0x438c UA0INTF UART3 Ch.0 Status and Interrupt Flag Register 0x438e UA0INTE UART3 Ch.0 Interrupt Enable Register 0x4390 UA0CAWF UART3 Ch.0 Carrier Waveform Register Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 54

    T16 Ch.2 Control Register 0x5266 T16_2TR T16 Ch.2 Reload Data Register 0x5268 T16_2TC T16 Ch.2 Counter Data Register 0x526a T16_2INTF T16 Ch.2 Interrupt Flag Register 0x526c T16_2INTE T16 Ch.2 Interrupt Enable Register Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 55

    *1 *2 *3 0x54ba ADC12_0AD7D ADC12A Ch.0 Result Register 7 *1 *2 *3 *1 Cannot be used in the S1C17M20/M23 (24-pin package). *2 Cannot be used in the S1C17M20/M23 (32-pin package). *3 Cannot be used in the S1C17M21/M24. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev.

  • Page 56: System-protect Function

    R/WP Always set to 0. 7–2 – 0x00 – – 1–0 RDWAIT[1:0] R/WP Bits 15–2 Reserved Bits 1–0 RDWAIT[1:0] These bits set the number of bus access cycles for reading from the Flash memory. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 57

    FLASHCWAIT.RDWAIT[1:0] bits Number of bus Access cycles System clock frequency 21.0 MHz (max.) 18.9 MHz (max.) 12.6 MHz (max.) 6.3 MHz (max.) Note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 58: Interrupt Controller (itc)

    Address misaligned interrupt Memory access instruction – (0xfffc00) Debugging interrupt brk instruction, etc. 2 (0x02) TTBR + 0x08 Watchdog timer overflow 3 (0x03) TTBR + 0x0c Reserved for C compiler – – Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 59

    R/F converter Ch.1 interrupt • Reference oscillation completion • Sensor A oscillation completion • Sensor B oscillation completion • Measurement counter overflow error • Time base counter overflow error 22 (0x16) TTBR + 0x58 16-bit timer Ch.2 interrupt Underflow Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 60: Vector Table Base Address (ttbr)

    Note: To prevent occurrence of unnecessary interrupts, the corresponding interrupt flag should be cleared before setting the interrupt enable bit to 1 (interrupt enabled) and before terminating the interrupt handler routine. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 61: Itc Interrupt Request Processing

    (0–7) to be set to the IL[2:0] bits in the PSR. The software inter- rupt cannot be disabled (non-maskable interrupt). The processor performs the same interrupt processing operation as that of the hardware interrupt. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 62: Interrupt Processing By The Cpu

    – 2–0 ILVy [2:0] Bits 15–11 Reserved Bits 7–3 Reserved = 2x +1) Bits 10–8 ILVy [2:0] = 2x) Bits 2–0 ILVy [2:0] These bits set the interrupt level of each interrupt. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 63

    (ILVREMC3_0) ITCLV8 15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV17[2:0] R/F converter Ch.1 interrupt Setup Register 8) (ILVRFC_1) 7–3 – 0x00 – – 2–0 ILV16[2:0] R/F converter Ch.0 interrupt (ILVRFC_0) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 64

    15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV21[2:0] – 12-bit A/D converter interrupt Setup Register 10) (ILVADC12A_0) 7–3 – 0x00 – – 2–0 ILV20[2:0] – 16-bit timer Ch.3 interrupt (ILVT16_3) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 65: I/o Ports (pport)

    Note: ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x = 0, 1, 2, ··· , d) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7). Figure 6.1.1 shows the configuration of PPORT. Table 6.1.1 Port Configuration of S1C17M20/M21/M22/M23/M24/M25 S1C17M20/M23 Item...

  • Page 66: I/o Cell Structure And Functions

    Figure 6.2.1 I/O Cell Configuration Refer to “Pin Descriptions” in the “Overview” chapter for the cell type, either the over voltage tolerant fail-safe type I/O cell or the standard I/O cell, included in each port. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 67: Schmitt Input

    (Clock division ratio selection = Clock frequency setting) 4. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection) Settings in Step 3 determine the input sampling time of the chattering filter. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 68: Clock Supply In Sleep Mode

    When using the Pxy port pin as a general-purpose output pin, perform the following software initial settings: 1. Set the PxIOEN.PxOENy bit to 1. (Enable output) 2. Set the PxMODSEL.PxSELy bit to 0. (Enable GPIO function) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 69: Port Input/output Control

    6.4.2 Port Input/Output Control Peripheral I/O function control The port for which a peripheral I/O function is selected is controlled by the peripheral circuit. For more infor- mation, refer to the respective peripheral circuit chapter. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 70

    Clearing PxINTF.PxIFy Interrupt edge selection Port input interrupts will occur at the falling edge of the input signal when setting the PxINTCTL.PxEDGEy bit to 1, or the rising edge when setting to 0. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 71: Control Registers

    *2: The bit configuration differs depending on the port group. Bits 15–8 PxIEN[7:0] These bits enable/disable the GPIO port input. 1 (R/W): Enable (The port pin status is input.) 0 (R/W): Disable (Input data is fixed at 0.) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 72: Px Port Pull-up/down Control Register

    Initial Reset Remarks PxINTCTL 15–8 PxEDGE[7:0] 0x00 – 7–0 PxIE[7:0] 0x00 *1: This register is effective when the GPIO function is selected. *2: The bit configuration differs depending on the port group. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 73: Px Port Chattering Filter Enable Register

    *1: The bit configuration differs depending on the port group. *2: The initial value may be changed by the port. Bits 15–14 Px7MUX[1:0] Bits 1–0 Px0MUX[1:0] These bits select the peripheral I/O function to be assigned to each port pin. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 74: P Port Clock Control Register

    The PPORT operating clock should be configured by selecting the clock source using the PCLK. CLKSRC[1:0] bits and the clock division ratio using the PCLK.CLKDIV[3:0] bits as shown in Table 6.6.3. These settings determine the input sampling time of the chattering filter. Seiko Epson Corporation 6-10 S1C17M20/M21/M22/M23/M24/M25...

  • Page 75: P Port Interrupt Flag Group Register

    A port generated an interrupt 0 (R): No port generated an interrupt The PINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 6-11 TECHNICAL MANUAL (Rev. 1.0)

  • Page 76: Control Register And Port Function Configuration Of This Ic

    ✓ P0OEN5 – – – ✓ P0OEN4 – – – ✓ P0OEN3 ✓ ✓ ✓ ✓ P0OEN2 ✓ ✓ ✓ ✓ P0OEN1 ✓ ✓ ✓ ✓ P0OEN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-12 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 77

    ✓ P0CHATEN5 – – – ✓ P0CHATEN4 – – – ✓ P0CHATEN3 ✓ ✓ ✓ ✓ P0CHATEN2 ✓ ✓ ✓ ✓ P0CHATEN1 ✓ ✓ ✓ ✓ P0CHATEN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 6-13 TECHNICAL MANUAL (Rev. 1.0)

  • Page 78: P1 Port Group

    ✓ P1IN5 ✓ ✓ ✓ ✓ P1IN4 ✓ ✓ ✓ ✓ P1IN3 ✓ ✓ ✓ ✓ P1IN2 ✓ ✓ ✓ ✓ P1IN1 – ✓ ✓ ✓ P1IN0 – ✓ ✓ ✓ Seiko Epson Corporation 6-14 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 79

    ✓ P1IE5 ✓ ✓ ✓ ✓ P1IE4 ✓ ✓ ✓ ✓ P1IE3 ✓ ✓ ✓ ✓ P1IE2 ✓ ✓ ✓ ✓ P1IE1 – ✓ ✓ ✓ P1IE0 – ✓ ✓ ✓ Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 6-15 TECHNICAL MANUAL (Rev. 1.0)

  • Page 80

    ✓ – – UPMUX – – – – – – – ✓ – – UPMUX – – – – – – – ✓ *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation 6-16 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 81: P2 Port Group

    ✓ P2REN5 ✓ ✓ ✓ ✓ P2REN4 ✓ ✓ ✓ ✓ P2REN3 – ✓ ✓ ✓ P2REN2 – ✓ ✓ ✓ P2REN1 – – – ✓ P2REN0 – – – ✓ Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 6-17 TECHNICAL MANUAL (Rev. 1.0)

  • Page 82

    ✓ 9–8 P24MUX[1:0] ✓ ✓ ✓ ✓ 7–6 P23MUX[1:0] – ✓ ✓ ✓ 5–4 P22MUX[1:0] – ✓ ✓ ✓ 3–2 P21MUX[1:0] – – – ✓ 1–0 P20MUX[1:0] – – – ✓ Seiko Epson Corporation 6-18 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 83: P3 Port Group

    ✓ P3OEN5 – – – ✓ P3OEN4 – – – ✓ P3OEN3 – – – ✓ P3OEN2 ✓ ✓ ✓ ✓ P3OEN1 ✓ ✓ ✓ ✓ P3OEN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 6-19 TECHNICAL MANUAL (Rev. 1.0)

  • Page 84

    ✓ P3CHATEN5 – – – ✓ P3CHATEN4 – – – ✓ P3CHATEN3 – – – ✓ P3CHATEN2 ✓ ✓ ✓ ✓ P3CHATEN1 ✓ ✓ ✓ ✓ P3CHATEN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-20 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 85: P4 Port Group

    ✓ P4IEN0 – – – ✓ 7–3 – 0x00 – – – – – – P4OEN2 – – – – ✓ P4OEN1 – – – ✓ P4OEN0 – – – ✓ Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 6-21 TECHNICAL MANUAL (Rev. 1.0)

  • Page 86

    – – – – ✓ RFC Ch.1 REF1 – – – – – – – – – ✓ RFC Ch.1 RFIN1 – – – – – – – – – ✓ Seiko Epson Corporation 6-22 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 87: Pd Port Group

    – – – – Register) PDSEL4 – – ✓ ✓ ✓ PDSEL3 – ✓ ✓ ✓ PDSEL2 ✓ ✓ ✓ ✓ PDSEL1 ✓ ✓ ✓ ✓ PDSEL0 ✓ ✓ ✓ ✓ Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 6-23 TECHNICAL MANUAL (Rev. 1.0)

  • Page 88: Common Registers Between Port Groups

    – – – Group Register) P4INT – – – – ✓ P3INT ✓ ✓ ✓ ✓ P2INT ✓ ✓ ✓ ✓ P1INT ✓ ✓ ✓ ✓ P0INT ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-24 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 89: Universal Port Multiplexer (upmux)

    4. Initialize the peripheral circuit. 5. Set the PxFNCSEL.PxyMUX[1:0] bits of the I/O port to 0x1. (Select peripheral I/O function 1) 6. Set the PxMODSEL.PxSELy bit of the I/O port to 1. (Enable peripheral I/O function) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 90

    Note: Do not assign a peripheral input function to two or more I/O ports. Although the I/O ports output the same waveforms when an output function is assigned to two or more I/O port, a skew oc- curs due to the internal delay. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 91: Watchdog Timer (wdt2)

    CLK_WDT2 supply is suspended, the register retains the status before DEBUG mode was entered. If the WDTCLK.DBRUN bit = 1, the CLK_WDT2 supply is not suspended and WDT2 will keep operating in DE- BUG mode. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 92

    1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection) 2. Write 0xa to the WDTCTL.WDTRUN[3:0] bits. (Stop WDT2) 3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 93: Operations In Halt And Sleep Modes

    IOSC OSC1 OSC3 EXOSC 1/65,536 1/128 1/65,536 1/32,768 1/32,768 1/16,384 1/16,384 1/8,192 1/8,192 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 94: Wdt2 Control Register

    WDT2 should also be reset concurrently when running WDT2. WDT2 Counter Compare Match Register Register name Bit name Initial Reset Remarks WDTCMP 15–10 – 0x00 – – 9–0 CMP[9:0] 0x3ff R/WP Bits 15–10 Reserved Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 95

    These bits set the NMI/reset generation cycle. The value set in this register is compared with the 10-bit counter value while WDT2 is running, and an NMI or reset is generated when they are matched. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 96: Real-time Clock (rtca)

    * Indicates the status when the pin is configured for RTCA. If the port is shared with the RTCA output function and other functions, the RTCA function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 97: Clock Settings

    · · · · · · · · · · · · · · · 0x3e 59.1 0x7e -1.9 0x3f 60.1 0x7f -1.0 Minimum resolution: 1 ppm, Correction rate range: -61.0 to 60.1 ppm Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 98

    3. Write 1 to the RTCINTF.ALARMIF bit to clear the alarm interrupt flag. 4. Write 1 to the RTCINTE.ALARMIE bit to enable alarm interrupts. When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 99: Real-time Clock Counter Operations

    9.4.4 Stopwatch Count-up Pattern The stopwatch consists of 1/100-second and 1/10-second counters and these counters perform counting up in incre- ments of approximate 1/100 and 1/10 seconds with the count-up patterns shown in Figure 9.4.4.1. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 100

    1 Hz counter value. • An alarm interrupt occurs after a lapse of 1/256 second from matching between the AM/PM (in 12H mode), hour, minute, and second counter value and the alarm setting value. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 101

    Depending on these operation timings, the +1 second correction may be executed after the count-up operation resumes. For more information on the +1 second correction, refer to “Real-Time Clock Counter Operations.” Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 102: Rtc Second Alarm Register

    The RTCALM1.RTCSHA[2:0] bits and the RTCALM1.RTCSLA[3:0] bits set the 10-second digit and 1-second digit of the alarm time, respectively. A value within 0 to 59 seconds can be set in BCD code as shown in Table 9.6.1. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 103: Rtc Hour/minute Alarm Register

    SWRUN Bits 15–12 BCD10[3:0] Bits 11–8 BCD100[3:0] The 1/10-second and 1/100-second digits of the stopwatch counter can be read as a BCD code from the RTCSWCTL.BCD10[3:0] bits and the RTCSWCTL.BCD100[3:0] bits, respectively. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 104: Rtc Second/1hz Register

    1-second digit of the second counter, respectively. The setting/read values are a BCD code within the range from 0 to 59. Note: Be sure to avoid writing to the RTCSEC.RTCSH[2:0]/RTCSL[3:0] bits while the RTCCTL.RT- CBSY bit = 1. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 105: Rtc Hour/minute Register

    1 to 12 in 12H mode or 0 to 23 in 24H mode. Note: Be sure to avoid writing to the RTCHUR.RTCHH[1:0]/RTCHL[3:0] bits while the RTCCTL. RTCBSY bit = 1. Bit 7 Reserved Seiko Epson Corporation 9-10 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 106: Rtc Month/day Register

    These bits are used to set and read day of the week. The day of the week counter is a base-7 counter and the setting/read values are 0x0 to 0x6. Table 9.6.2 lists the correspondence between the count value and day of the week. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 9-11...

  • Page 107: Rtc Interrupt Flag Register

    The following shows the correspondence between the bit and interrupt: RTCINTF.RTCTRMIF bit: Theoretical regulation completion interrupt RTCINTF.SW1IF bit: Stopwatch 1 Hz interrupt RTCINTF.SW10IF bit: Stopwatch 10 Hz interrupt RTCINTF.SW100IF bit: Stopwatch 100 Hz interrupt Bits 11–9 Reserved Seiko Epson Corporation 9-12 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 108: Rtc Interrupt Enable Register

    The following shows the correspondence between the bit and interrupt: RTCINTE.RTCTRMIE bit: Theoretical regulation completion interrupt RTCINTE.SW1IE bit: Stopwatch 1 Hz interrupt RTCINTE.SW10IE bit: Stopwatch 10 Hz interrupt RTCINTE.SW100IE bit: Stopwatch 100 Hz interrupt Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 9-13 TECHNICAL MANUAL (Rev. 1.0)

  • Page 109

    RTCINTE.1DAYIE bit: 1-day interrupt RTCINTE.1HURIE bit: 1-hour interrupt RTCINTE.1MINIE bit: 1-minute interrupt RTCINTE.1SECIE bit: 1-second interrupt RTCINTE.1_2SECIE bit: 1/2-second interrupt RTCINTE.1_4SECIE bit: 1/4-second interrupt RTCINTE.1_8SECIE bit: 1/8-second interrupt RTCINTE.1_32SECIE bit: 1/32-second interrupt Seiko Epson Corporation 9-14 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 110: Supply Voltage Detector (svd3)

    - Low power supply voltage detection count function to generate an inter- rupt/reset when low power supply voltage is successively detected the number of times specified. - Continuous operation is also possible. Figure 10.1.1 shows the configuration of SVD3. Table 10.1.1 SVD3 Configuration of S1C17M20/M21/M22/M23/M24/M25 S1C17M20/M23 Item S1C17M21/M24 S1C17M22/M25...

  • Page 111: Input Pins And External Connection

    If the CLGOSC.xxxxSLPC bit for the CLK_SVD3 clock source is 1, the CLK_SVD3 clock source is deactivated during SLEEP mode and SVD3 stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD3 is supplied and the SVD3 operation resumes. Seiko Epson Corporation 10-2 S1C17M20/M21/M22/M23/M24/M25...

  • Page 112: Clock Supply In Debug Mode

    SVDCTL.MODEN bit = 1, wait for at least SVD circuit response time be- SVD_EXT fore reading the SVDINTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time t ” in the “Electrical Characteristics” chapter). Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 10-3 TECHNICAL MANUAL (Rev. 1.0)

  • Page 113: Svd3 Operations

    SVDIF bit). An interrupt request is sent to the interrupt controller only when the SVDINTF.SVDIF bit is set while the interrupt is enabled by the SVDINTE.SVDIE bit. For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 10-4 S1C17M20/M21/M22/M23/M24/M25...

  • Page 114: Svd3 Reset

    Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SVD3 operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SVD3. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 10-5 TECHNICAL MANUAL (Rev. 1.0)

  • Page 115: Svd3 Control Register

    0x01 ↓ 0x00 For the configurable range and voltage values, refer to “Supply Voltage Detector Characteristics, SVD detection voltage V /EXSVD detection voltage V ” in the “Electrical Characteristics” chapter. SVD_EXT Seiko Epson Corporation 10-6 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 116: Svd3 Status And Interrupt Flag Register

    EXSVD0/1) < SVD detection voltage V or EXSVD detection voltage V SVD_EXT or EXSVD0/1) ≥ SVD detection voltage V 0 (R): Power supply voltage (V or EXSVD detection voltage V SVD_EXT Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 10-7 TECHNICAL MANUAL (Rev. 1.0)

  • Page 117: Svd3 Interrupt Enable Register

    • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 10-8 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 118: Bit Timers (t16)

    • A clock source and clock division ratio for generating the count clock are selectable. • Repeat mode or one-shot mode is selectable. • Can generate counter underflow interrupts. Figure 11.1.1 shows the configuration of a T16 channel. Table 11.1.1 T16 Channel Configuration of S1C17M20/M21/M22/M23/M24/M25 S1C17M20/M23 Item S1C17M21/M24...

  • Page 119

    (Set reload data (counter preset data)) 5. Set the following bits when using the interrupt: - Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag) - Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt) Seiko Epson Corporation 11-2 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 120: Counter Underflow

    At the same time the counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 11-3...

  • Page 121: Counter Value Read

    Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16 Ch.n operating clock (counter clock). Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of T16 Ch.n. Seiko Epson Corporation 11-4 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 122: T16 Ch.n Mode Register

    PRESET MODEN Bits 15–9 Reserved Bit 8 PRUN This bit starts/stops the timer. 1 (W): Start timer 0 (W): Stop timer 1 (R): Timer is running 0 (R): Timer is idle Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 11-5 TECHNICAL MANUAL (Rev. 1.0)

  • Page 123: T16 Ch.n Reload Data Register

    This bit indicates the T16 Ch.n underflow interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 11-6 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 124: T16 Ch.n Interrupt Enable Register

    This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 11-7 TECHNICAL MANUAL (Rev. 1.0)

  • Page 125

    • Input pin can be pulled up with an internal resistor. • The output pin is configurable as an open-drain output. • Provides the carrier modulation output function. Figure 12.1.1 shows the UART3 configuration. Table 12.1.1 UART3 Channel Configuration of S1C17M20/M21/M22/M23/M24/M25 S1C17M20/M23 Item S1C17M21/M24...

  • Page 126: Input/output Pins And External Connections

    - UAnCLK.CLKSRC[1:0] bits (Clock source selection) - UAnCLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting) The UART3 operating clock should be selected so that the baud rate generator will be configured easily. Seiko Epson Corporation 12-2 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 127

    (UAnMOD.STPB bit = 1). Parity function The parity function is configured using the UAnMOD.PREN and UAnMOD.PRMD bits. Table 12.4.1 Parity Function Setting UAnMOD.PREN bit UAnMOD.PRMD bit Parity function Odd parity Even parity Non parity Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 12-3 TECHNICAL MANUAL (Rev. 1.0)

  • Page 128

    - Set the interrupt enable bits in the UAnINTE register to 1. * (Enable interrupts) * The initial value of the UAnINTF.TBEIF bit is 1, therefore, an interrupt will occur immediately after the UA- nINTE.TBEIE bit is set to 1. Seiko Epson Corporation 12-4 S1C17M20/M21/M22/M23/M24/M25...

  • Page 129: Data Transmission

    Read the UAnINTF.TBEIF bit UAnINTF.TBEIF = 1 ? Write transmit data to the UAnTXD register Transmit data remained? Wait for an interrupt request (UAnINTF.TBEIF = 1) Figure 12.5.2.2 Data Transmission Flowchart Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 12-5 TECHNICAL MANUAL (Rev. 1.0)

  • Page 130: Data Reception

    Read receive data (1 byte) from the UAnRXD register the UAnRXD register Read receive data (1 byte) from the UAnRXD register Receive data remained? Receive data remained? Figure 12.5.3.2 Data Reception Flowcharts Seiko Epson Corporation 12-6 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 131: Irda Interface

    Writing 1 to the UAnMOD.CAREN bit enables the carrier modulation function allowing carrier modulation wave- forms to be output according to the UAnMOD.PECAR bit setting. Data transmit control is identical to that for nor- mal interface even in this case. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 12-7...

  • Page 132: Receive Errors

    The received data that encountered an error is still transferred to the receive data buffer and the UAnINTF.PEIF bit (parity error interrupt flag) is set to 1 when the data becomes ready to read from the UAnRXD register (see the Note on framing error). Seiko Epson Corporation 12-8 S1C17M20/M21/M22/M23/M24/M25...

  • Page 133: Overrun Error

    1 (R/W): Clock supplied in DEBUG mode 0 (R/W): No clock supplied in DEBUG mode Bits 7–6 Reserved Bits 5–4 CLKDIV[1:0] These bits select the division ratio of the UART3 operating clock. Bits 3–2 Reserved Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 12-9 TECHNICAL MANUAL (Rev. 1.0)

  • Page 134: Uart3 Ch.n Mode Register

    0 (R/W): Disable input inverting function Bit 8 INVTX This bit enables the USOUTn output inverting function. 1 (R/W): Enable output inverting function 0 (R/W): Disable output inverting function Bit 7 Reserved Seiko Epson Corporation 12-10 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 135: Uart3 Ch.n Baud–rate Register

    Notes: • The UAnBR register settings can be altered only when the UAnCTL.MODEN bit = 0. • Do not set the UAnBR.FMD[3:0] bits to a value other than 0 to 3 when the UAnMOD.BRDIV bit = 1. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 12-11...

  • Page 136: Uart3 Ch.n Control Register

    Bits 15–8 Reserved Bits 7–0 RXD[7:0] The receive data buffer can be read through these bits. The receive data buffer consists of a 2-byte FIFO, and older received data is read first. Seiko Epson Corporation 12-12 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 137: Uart3 Ch.n Status And Interrupt Flag Register

    UAnINTF.PEIF bit: Parity error interrupt UAnINTF.OEIF bit: Overrun error interrupt UAnINTF.RB2FIF bit: Receive buffer two bytes full interrupt UAnINTF.RB1FIF bit: Receive buffer one byte full interrupt UAnINTF.TBEIF bit: Transmit buffer empty interrupt Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 12-13 TECHNICAL MANUAL (Rev. 1.0)

  • Page 138: Uart3 Ch.n Interrupt Enable Register

    UAnCAWF 15–8 – 0x00 – – 7–0 CRPER[7:0] 0x00 Bits 15–8 Reserved Bits 7–0 CRPER[7:0] These bits set the carrier modulation output frequency. For more information, refer to “Carrier Modu- lation.” Seiko Epson Corporation 12-14 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 139

    • Slave mode is capable of being operated in SLEEP mode allowing wake-up by an SPIA interrupt. • Input pins can be pulled up/down with an internal resistor. Figure 13.1.1 shows the SPIA configuration. Table 13.1.1 SPIA Channel Configuration of S1C17M20/M21/M22/M23/M24/M25 S1C17M20/M23 Item...

  • Page 140

    SDIn #SPISS0 SPICLKn #SPISS1 #SPISS #SPISS2 External SPI master device External SPI slave devices SPICLK SPICLK #SPISS SPICLK Figure 13.2.2.2 Connections between SPIA in Slave Mode and External SPI Master Device Seiko Epson Corporation 13-2 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 141: Pin Functions In Master Mode And Slave Mode

    16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro- priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated by the equations shown below. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 13-3...

  • Page 142

    SDIn SDOn (Master mode) SDOn (Slave mode) SDOn (Slave mode) Writing data to the SPInTXD register Figure 13.3.3.1 SPI Clock Phase and Polarity (SPInMOD.LSBFST bit = 0, SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 13-4 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 143: Data Format

    1. Assert the slave select signal by controlling the general-purpose output port (if necessary). 2. Check to see if the SPInINTF.TBEIF bit is set to 1 (transmit buffer empty). 3. Write transmit data to the SPInTXD register. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 13-5...

  • Page 144

    SPInTXD register Transmit data remained? Wait for an interrupt request (SPInINTF.TBEIF = 1) Negate the slave select signal output from a general-purpose port Figure 13.5.2.2 Data Transmission Flowchart in Master Mode Seiko Epson Corporation 13-6 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 145: Data Reception In Master Mode

    Software operations SPInRXD → Data (R) Data (W) → SPInTXD SPInRXD → Data (R) 1 (W) → SPInINTF.TENDIF Figure 13.5.3.1 Example of Data Receiving Operations in Master Mode (SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 13-7 TECHNICAL MANUAL (Rev. 1.0)

  • Page 146: Terminating Data Transfer In Master Mode

    SPInTXD register data written is completed. If no transmit data is written during this period, the data bits input from the SDIn pin are shifted and output from the SDOn pin without being modified. Seiko Epson Corporation 13-8 S1C17M20/M21/M22/M23/M24/M25...

  • Page 147

    Data (W) → SPInTXD Data (W) → SPInTXD Software operations SPInRXD → Data (R) SPInRXD → Data (R) Figure 13.5.5.1 Example of Data Transfer Operations in Slave Mode (SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 13-9 TECHNICAL MANUAL (Rev. 1.0)

  • Page 148: Terminating Data Transfer In Slave Mode

    “Interrupt Controller” chapter. The SPInINTF register also contains the BSY bit that indicates the SPIA operating status. Figure 13.6.1 shows the SPInINTF.BSY and SPInINTF.TENDIF bit set timings. Seiko Epson Corporation 13-10 S1C17M20/M21/M22/M23/M24/M25...

  • Page 149

    Remarks SPInMOD 15–12 – – – 11–8 CHLN[3:0] 7–6 – – PUEN NOCLKDIV LSBFST CPHA CPOL Bits 15–12 Reserved Bits 11–8 CHLN[3:0] These bits set the bit length of transfer data. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 13-11 TECHNICAL MANUAL (Rev. 1.0)

  • Page 150: Spia Ch.n Control Register

    Note: The SPInMOD register settings can be altered only when the SPInCTL.MODEN bit = 0. SPIA Ch.n Control Register Register name Bit name Initial Reset Remarks SPInCTL 15–8 – 0x00 – – 7–2 – 0x00 – SFTRST MODEN Bits 15–2 Reserved Seiko Epson Corporation 13-12 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 151: Spia Ch.n Transmit Data Register

    0x00 – – 6–4 – – OEIF H0/S0 Cleared by writing 1. TENDIF H0/S0 RBFIF H0/S0 Cleared by reading the SPInRXD register. TBEIF H0/S0 Cleared by writing to the SPInTXD register. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 13-13 TECHNICAL MANUAL (Rev. 1.0)

  • Page 152: Spia Ch.n Interrupt Enable Register

    The following shows the correspondence between the bit and interrupt: SPInINTE.OEIE bit: Overrun error interrupt SPInINTE.TENDIE bit: End-of-transmission interrupt SPInINTE.RBFIE bit: Receive buffer full interrupt SPInINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 13-14 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 153

    • Master mode supports automatic bus clear sending function. • Can generate receive buffer full, transmit buffer empty, and other interrupts. Figure 14.1.1 shows the I2C configuration. Table 14.1.1 I2C Channel Configuration of S1C17M20/M21/M22/M23/M24/M25 S1C17M20/M23 Item S1C17M21/M24...

  • Page 154

    • The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I bus. Seiko Epson Corporation 14-2 S1C17M20/M21/M22/M23/M24/M25...

  • Page 155

    14.3.3.1). Note: The I C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do not set a transfer rate exceeding the limit. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 14-3 TECHNICAL MANUAL (Rev. 1.0)

  • Page 156

    - Set the I2CnCTL.MST bit to 0. (Set slave mode) - Set the I2CnCTL.SFTRST bit to 1. (Execute software reset) - Set the I2CnCTL.MODEN bit to 1. (Enable I2C Ch.n operations) Seiko Epson Corporation 14-4 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 157: Data Transmission In Master Mode

    I2CnINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condition. When the repeated START condition has been generated, the I2CnINTF.STARTIF and I2CnINTF.TBEIF bits are both set to 1 same as when a START condition has been generated. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 14-5...

  • Page 158

    Last data sent? Retry? Write 1 to the I2CnCTL.TXSTOP bit Write data to the I2CnTXD register Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 14.4.2.2 Master Mode Data Transmission Flowchart Seiko Epson Corporation 14-6 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 159

    This reading triggers the I2C Ch.n to start subsequent data reception. Generating a STOP or repeated START condition It is the same as the data transmission in master mode. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 14-7 TECHNICAL MANUAL (Rev. 1.0)

  • Page 160

    Read receive data from the I2CnRXD register Write 1 to the I2CnCTL.TXSTOP bit Write 1 to the I2CnCTL.TXSTOP bit Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 14.4.3.2 Master Mode Data Reception Flowchart Seiko Epson Corporation 14-8 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 161: Bit Addressing In Master Mode

    Clear the I2CnINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2CnTXD.TXD[7:1] bits and 1 that represents READ as the data transfer direc- tion to the I2CnTXD.TXD0 bit. 10. Perform data reception. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 14-9 TECHNICAL MANUAL (Rev. 1.0)

  • Page 162: Data Transmission In Slave Mode

    Go to Step 6 when a STOP condition interrupt has occurred. ii. Go to Step 2 when a START condition interrupt has occurred. 6. Clear the I2CnINTF.STOPIF bit and then terminate data sending operations. Seiko Epson Corporation 14-10 S1C17M20/M21/M22/M23/M24/M25...

  • Page 163

    A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0), STARTIF = 1 Data n: 8-bit data Figure 14.4.5.1 Example of Data Sending Operations in Slave Mode Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 14-11 TECHNICAL MANUAL (Rev. 1.0)

  • Page 164: Data Reception In Slave Mode

    I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred to the receive data buffer and the I2CnINTF.RBFIF and I2CnINTF.BYTEENDIF bits are both set to 1. Af- ter that, the received data can be read out from the I2CnRXD register. Seiko Epson Corporation 14-12 S1C17M20/M21/M22/M23/M24/M25...

  • Page 165

    Wait for an interrupt request (I2CnINTF.RBFIF = 1) Last data received next? Write 1 to the I2CnCTL.TXNACK bit Read receive data from the I2CnRXD register Last data received? Figure 14.4.6.2 Slave Mode Data Reception Flowchart Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 14-13 TECHNICAL MANUAL (Rev. 1.0)

  • Page 166: Slave Operations In 10-bit Address Mode

    If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2CnCTL.TXSTART bit to 0 and sets both the I2CnINTF.ERRIF and I2CnINTF.STARTIF bits to 1. Seiko Epson Corporation 14-14 S1C17M20/M21/M22/M23/M24/M25...

  • Page 167: Error Detection

    4 <Master mode only> When 1 is written to the I2CnCTL.TX- I2CnINTF.ERRIF = 1 START bit while the I2CnINTF.BSY bit = 0 (Refer to “Automatic Automatic bus clearing I2CnCTL.TXSTART = 0 Bus Clearing Operation.”) failure I2CnINTF.STARTIF = 1 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 14-15 TECHNICAL MANUAL (Rev. 1.0)

  • Page 168

    Master mode BRT + 3 CLK_I2Cn TXSTART = 1 TXSTART = 0 STARTIF = 1 Slave mode Address matching the I2CnOADR register BSY = 1 TR = 0/1 STARTIF = 1 Seiko Epson Corporation 14-16 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 169

    (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Note: The I2CnCLK register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 14-17 TECHNICAL MANUAL (Rev. 1.0)

  • Page 170: I2c Ch.n Mode Register

    The I2CnOADR.OADR[9:0] bits are effective in 10-bit address mode (I2CnMOD.OADR10 bit = 1), or the I2CnOADR.OADR[6:0] bits are effective in 7-bit address mode (I2CnMOD.OADR10 bit = 0). Note: The I2CnOADR register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation 14-18 S1C17M20/M21/M22/M23/M24/M25...

  • Page 171: I2c Ch.n Control Register

    Bit 0 MODEN This bit enables the I2C operations. 1 (R/W): Enable I2C operations (The operating clock is supplied.) 0 (R/W): Disable I2C operations (The operating clock is stopped.) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 14-19 TECHNICAL MANUAL (Rev. 1.0)

  • Page 172: I2c Ch.n Transmit Data Register

    0 (R): SDA = High level Bit 11 SCLLOW This bit indicates that SCL is set to low level. 1 (R): SCL = Low level 0 (R): SCL = High level Seiko Epson Corporation 14-20 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 173: I2c Ch.n Interrupt Enable Register

    Transmit buffer empty interrupt I2C Ch.n Interrupt Enable Register Register name Bit name Initial Reset Remarks I2CnINTE 15–8 – 0x00 – – BYTEENDIE GCIE NACKIE STOPIE STARTIE ERRIE RBFIE TBEIE Bits 15–8 Reserved Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 14-21 TECHNICAL MANUAL (Rev. 1.0)

  • Page 174

    I2CnINTE.NACKIE bit: NACK reception interrupt I2CnINTE.STOPIE bit: STOP condition interrupt I2CnINTE.STARTIE bit: START condition interrupt I2CnINTE.ERRIE bit: Error detection interrupt I2CnINTE.RBFIE bit: Receive buffer full interrupt I2CnINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 14-22 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 175

    - The capture circuit captures counter values using external/software trigger signals and generates interrupts. (Can be used to measure external event periods/cycles.) Figure 15.1.1 shows the T16B configuration. Table 15.1.1 T16B Channel Configuration of S1C17M20/M21/M22/M23/M24/M25 S1C17M20/M23 Item S1C17M21/M24 S1C17M22/M25...

  • Page 176

    * Indicates the status when the pin is configured for T16B. If the port is shared with the T16B pin and other functions, the T16B input/output function must be assigned to the port before activating T16B. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation 15-2 S1C17M20/M21/M22/M23/M24/M25...

  • Page 177

    Figure 15.3.4.1 Count Timing (During Count Up Operation) Note: When running the counter using the event counter clock, two dummy clocks must be input be- fore the first counting up/down can be performed. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 15-3 TECHNICAL MANUAL (Rev. 1.0)

  • Page 178

    - T16BnCTL.CNTMD[1:0] bits (Select count up/down operation) - T16BnCTL.ONEST bit (Select one-shot/repeat operation) - Set the T16BnCTL.PRESET bit to 1. (Reset counter) - Set the T16BnCTL.RUN bit to 1. (Start counting) Seiko Epson Corporation 15-4 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 179: Counter Block Operations

    MAX value. If the MAX value is altered to a value smaller than the current counter value, the counter is cleared to 0x0000 and continues counting up to the new MAX value. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 15-5...

  • Page 180

    MODEN = 1 PRESET = 1 RUN = 1 Software operation Data (W) → MC[15:0] RUN = 1 RUN = 0 Hardware operation 0xffff Count cycle MAX value Counter Time 0x0000 Seiko Epson Corporation 15-6 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 181

    Data (W) → MC[15:0] RUN = 1 RUN = 1 0xffff MAX value Counter Time 0x0000 RUN = 0 Figure 15.4.2.3 Operations in Repeat Up/Down Count and One-shot Up/Down Count Modes Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 15-7 TECHNICAL MANUAL (Rev. 1.0)

  • Page 182: Comparator/capture Block Operations

    MAX value (T16BnMC register) Counter Comparison value (T16BnCCRm register) Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-8 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 183

    (T16BnMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 15-9 TECHNICAL MANUAL (Rev. 1.0)

  • Page 184

    (T16BnMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-10 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 185

    (T16BnMC register) Counter Compare buffer value Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 15-11 TECHNICAL MANUAL (Rev. 1.0)

  • Page 186

    (T16BnMC register) Counter Compare buffer value Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-12 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 187

    Compare period during counting down Time 0x0000 CNTMAXIF = 1 CNTZEROIF = 1 CNTMAXIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 15-13 TECHNICAL MANUAL (Rev. 1.0)

  • Page 188

    If the captured data stored in the T16BnCCRm register is overwritten by the next trigger when the T16BnINTF. CMPCAPmIF bit is still set, an overwrite error occurs (the T16BnINTF.CAPOWmIF bit is set). Seiko Epson Corporation 15-14 S1C17M20/M21/M22/M23/M24/M25...

  • Page 189

    Capture trigger signal T16BnCCRm.CC[15:0] Capturing operation (2) Asynchronous capture mode (When T16BnCCCTLm.CAPTRG[1:0] bits = 0x3) Count clock T16BnTC.TC[15:0] Capture trigger signal T16BnCCRm.CC[15:0] Capturing operation Figure 15.4.3.4 Synchronous Capture Mode/Asynchronous Capture Mode Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 15-15 TECHNICAL MANUAL (Rev. 1.0)

  • Page 190: Tout Output Control

    The TOUT signal polarity (active level) can be set using the T16BnCCCTLm.TOUTINV bit. It is set to active high by setting the T16BnCCCTLm.TOUTINV bit to 0 and active low by setting to 1. Figures 15.4.4.2 and 15.4.4.3 show the TOUT output waveforms. Seiko Epson Corporation 15-16 S1C17M20/M21/M22/M23/M24/M25...

  • Page 191

    Software control mode (0x0) Set mode (0x1) Toggle/reset mode (0x2) Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 15-17 TECHNICAL MANUAL (Rev. 1.0)

  • Page 192

    Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Figure 15.4.4.2 TOUT Output Waveform (T16BnCCCTLm.TOUTMT bit = 0) Seiko Epson Corporation 15-18 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 193

    Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 15-19 TECHNICAL MANUAL (Rev. 1.0)

  • Page 194

    Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 15-20 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 195

    Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Figure 15.4.4.3 TOUT Output Waveform (T16BnCCCTL0.TOUTMT bit = 1, T16BnCCCTL1.TOUTMT bit = 0) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 15-21 TECHNICAL MANUAL (Rev. 1.0)

  • Page 196: Interrupt

    Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16B Ch.n operating clock (counter clock). Bit 3 Reserved Bits 2–0 CLKSRC[2:0] These bits select the clock source of T16B Ch.n. Seiko Epson Corporation 15-22 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 197: T16b Ch.n Counter Control Register

    T16BnCTL.ONEST bit setting (see Table 15.6.2). Bit 3 ONEST This bit selects the counter repeat/one-shot mode. The count mode is configured with this selection and the T16BnCTL.CNTMD[1:0] bit settings (see Table 15.6.2). Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 15-23 TECHNICAL MANUAL (Rev. 1.0)

  • Page 198: T16b Ch.n Max Counter Data Register

    T16BnCTL.MODEN bit to 1 until the T16BnCS.BSY bit is set to 0 from 1. • Do not set the T16BnMC.MC[15:0] bits to 0x0000. T16B Ch.n Timer Counter Data Register Register name Bit name Initial Reset Remarks T16BnTC 15–0 TC[15:0] 0x0000 – Seiko Epson Corporation 15-24 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 199: T16b Ch.n Counter Status Register

    This bit indicates the currently set count direction. 1 (R): Count up 0 (R): Count down Bit 0 This bit indicates the counter operating status. 1 (R): Running 0 (R): Idle Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 15-25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 200: T16b Ch.n Interrupt Flag Register

    Note: The configuration of the T16BnINTF.CAPOWmIF and T16BnINTF.CMPCAPmIF bits depends on the model. The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. Seiko Epson Corporation 15-26 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 201: T16b Ch.n Interrupt Enable Register

    The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 15-27 TECHNICAL MANUAL (Rev. 1.0)

  • Page 202: T16b Ch.n Comparator/capture M Control Register

    These bits select the trigger edge(s) of the trigger signal at which the counter value is captured in the T16BnCCRm register in capture mode (see Table 15.6.4). The T16BnCCCTLm.CAPTRG[1:0] bits are control bits for capture mode and are ineffective in comparator mode. Seiko Epson Corporation 15-28 S1C17M20/M21/M22/M23/M24/M25...

  • Page 203

    The signal becomes inactive by the MATCH signal. All count modes TOUTnm The signal becomes inactive by the MATCHm or MATCHm+1 signal. TOUTnm+1 The signal becomes inactive by the MATCHm+1 or MATCHm signal. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 15-29 TECHNICAL MANUAL (Rev. 1.0)

  • Page 204: T16b Ch.n Compare/capture M Data Register

    In capture mode, this register is configured as the capture register and the counter value captured by the capture trigger signal is loaded. Seiko Epson Corporation 15-30 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 205

    Clock generator DBRUN MODEN SBSY Sound register MOSEL[1:0] Sound generation STIM[3:0] circuit BZOUT SINV Output control circuit SSTP #BZOUT Interrupt controller Interrupt control circuit EMIE EMIF EDIE EDIF Figure 16.1.1 SNDA Configuration Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 16-1 TECHNICAL MANUAL (Rev. 1.0)

  • Page 206: Output Pins And External Connections

    Piezoelectric buzzer #BZOUT S1C17 SNDA Figure 16.2.2.1 Connection between SNDA and Piezoelectric Buzzer (Direct Drive) Piezoelectric buzzer BZOUT S1C17 SNDA Figure 16.2.2.2 Connection between SNDA and Piezoelectric Buzzer (Single Pin Drive) Seiko Epson Corporation 16-2 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 207

    IC. The buzzer output duration can also be controlled via software. An output start/stop procedure and the SNDA operations are shown below. Normal buzzer output start/stop procedure 1. Set the SNDSEL.MOSEL[1:0] bits to 0x0. (Set normal buzzer mode) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 16-3 TECHNICAL MANUAL (Rev. 1.0)

  • Page 208

    Buzzer signal frequency [Hz] BZOUT DUTY: Buzzer signal duty ratio [%] However, the following settings are prohibited: • Settings as SNDDAT.SFRQ[7:0] bits ≤ SNDDAT.SLEN[5:0] bits • Settings as SNDDAT.SFRQ[7:0] bits = 0x00 Seiko Epson Corporation 16-4 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 209

    – 71.9 35.9 0x15 – – – – 68.8 34.4 0x14 – – – – 65.6 32.8 0x13 – – – – 62.5 31.3 0x12 – – – – 59.4 29.7 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 16-5 TECHNICAL MANUAL (Rev. 1.0)

  • Page 210: Buzzer Output In One-shot Buzzer Mode

    At the same time, the SNDINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SND- INTF.SBSY bit is cleared to 0. Figure 16.4.3.1 shows a buzzer output timing chart in one-shot buzzer mode. Seiko Epson Corporation 16-6 S1C17M20/M21/M22/M23/M24/M25...

  • Page 211: Output In Melody Mode

    At the same time, the SNDINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SNDINTF.SBSY bit is cleared to 0. Figure 16.4.4.1 shows a melody mode operation timing chart. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 16-7 TECHNICAL MANUAL (Rev. 1.0)

  • Page 212

    = 32,768 Hz) CLK_SNDA SNDDAT.SFRQ[7:0] bits Scale Frequency [Hz] 0xf8 131.60 0xea 139.44 0xdd 147.60 0xd1 156.04 0xc5 165.49 0xba 175.23 0xaf 186.18 0xa5 197.40 0x9c 208.71 0x93 221.41 0x8b 234.06 Seiko Epson Corporation 16-8 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 213

    This bit sets whether the SNDA operating clock is supplied in DEBUG mode or not. 1 (R/W): Clock supplied in DEBUG mode 0 (R/W): No clock supplied in DEBUG mode Bit 7 Reserved Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 16-9 TECHNICAL MANUAL (Rev. 1.0)

  • Page 214: Snda Select Register

    187.5 43.6 171.9 156.3 53.3 140.6 125.0 68.6 109.4 93.8 78.1 62.5 46.9 31.3 15.6 Note: Be sure to avoid altering these bits when SNDINTF.SBSY bit = 1. Bits 7–3 Reserved Seiko Epson Corporation 16-10 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 215: Snda Control Register

    This bit specifies a tie or slur (continuous play with the previous note) in melody mode. 1 (R/W): Enable tie/slur 0 (R/W): Disable tie/slur This bit is ignored in normal buzzer mode/one-shot buzzer mode. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 16-11 TECHNICAL MANUAL (Rev. 1.0)

  • Page 216: Snda Interrupt Flag Register

    No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective The following shows the correspondence between the bit and interrupt: SNDINTF.EMIF bit: Sound buffer empty interrupt SNDINTF.EDIF bit: Sound output completion interrupt Seiko Epson Corporation 16-12 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 217: Snda Interrupt Enable Register

    These bits enable SNDA interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts The following shows the correspondence between the bit and interrupt: SNDINTE.EMIE bit: Sound buffer empty interrupt SNDINTE.EDIE bit: Sound output completion interrupt Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 16-13 TECHNICAL MANUAL (Rev. 1.0)

  • Page 218

    • Automatic data setting function for continuous data transmission. • Output signal inverting function supporting various formats. • EL lamp drive waveform can be generated for an application example. Figure 17.1.1 shows the REMC3 configuration. Table 17.1.1 REMC3 Channel Configuration of S1C17M20/M21/M22/M23/M24/M25 S1C17M20/M23 Item S1C17M21/M24...

  • Page 219: External Connections

    1. Write 1 to the REMDBCTL.REMCRST bit. (Reset REMC3) 2. Configure the REMCLK.CLKSRC[1:0] and REMCLK.CLKDIV[3:0] bits. (Configure operating clock) 3. Assign the REMC3 output function to the port. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation 17-2 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 220: Data Transmission Procedures

    The REMC3 outputs the logical AND between the carrier signal output from the carrier generator and the data sig- nal output from the data signal generator. Figure 17.4.3.1 shows an example of the output waveform. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 17-3...

  • Page 221

    The data signal is generated by comparing the values of the 16-bit counter for data signal generation (REM- DBCNT.DBCNT[15:0] bits) that runs with CLK_REMC3 and the setting values of the REMAPLEN. APLEN[15:0] and REMDBLEN.DBLEN[15:0] bits. Figure 17.4.3.3 shows an example of the data signal gen- erated. Seiko Epson Corporation 17-4 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 222: Continuous Data Transmission And Compare Buffers

    (REMDBCTL.TRMD bit = 1), the counter stops automatically when the counter value is matched with the REMDBLEN.DBLEN[15:0] bit-setting value. 17.4.4 Continuous Data Transmission and Compare Buffers Figure 17.4.4.1 shows an operation example of continuous data transmission with the compare buffer enabled. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 17-5 TECHNICAL MANUAL (Rev. 1.0)

  • Page 223

    The REMC3 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the in- terrupt controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 17-6 S1C17M20/M21/M22/M23/M24/M25...

  • Page 224: Application Example: Driving El Lamp

    1 (R/W): Clock supplied in DEBUG mode 0 (R/W): No clock supplied in DEBUG mode Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the REMC3 operating clock. Bits 3–2 Reserved Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 17-7 TECHNICAL MANUAL (Rev. 1.0)

  • Page 225: Remc3 Data Bit Counter Control Register

    This bit starts/stops counting by the internal counters (16-bit counter for data signal generation and 8-bit counter for carrier generation). 1 (W): Start counting 0 (W): Stop counting 1 (R): Counting 0 (R): Idle Seiko Epson Corporation 17-8 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 226: Remc3 Data Bit Counter Register

    0x0000 H0/S0 Cleared by writing 1 to the REMDBCTL.REMCRST bit. Bits 15–0 DBCNT[15:0] The current value of the 16-bit counter for data signal generation can be read out through these bits. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 17-9 TECHNICAL MANUAL (Rev. 1.0)

  • Page 227: Remc3 Data Bit Active Pulse Length Register

    Transfer to the REMAPLEN buffer has not completed. 0 (R): Transfer to the REMAPLEN buffer has completed. While this bit is set to 1, writing to the REMAPLEN.APLEN[15:0] bits is ineffective. Seiko Epson Corporation 17-10 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 228: Remc3 Interrupt Enable Register

    These bits set the carrier signal cycle. A carrier signal cycle begins with the 8-bit counter for carrier generation = 0x00 and ends when the counter exceeds the REMCARR.CRPER[7:0] bit-setting value. (See Figure 17.4.3.2.) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 17-11 TECHNICAL MANUAL (Rev. 1.0)

  • Page 229: Remc3 Carrier Modulation Control Register

    This bit enables carrier modulation. 1 (R/W): Enable carrier modulation 0 (R/W): Disable carrier modulation (output data signal only) Note: When carrier modulation is disabled, the REMDBCTL.REMOINV bit should be set to 0. Seiko Epson Corporation 17-12 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 230: R/f Converter (rfc)

    • Provides an output and continuous oscillation function for monitoring the oscillation frequency. • Can generate reference oscillation completion, sensor (A and B) oscillation completion, measurement counter overflow error, and time base counter overflow error interrupts. Figure 18.1.1 shows the RFC configuration. Table 18.1.1 RFC Channel Configuration of S1C17M20/M21/M22/M23/M24/M25 S1C17M20/M23 Item S1C17M21/M24...

  • Page 231

    Figure 18.2.2.1 Connection Example in Resistive Sensor DC Oscillation Mode SENBn SEN1 SENAn REFn RFINn : Reference resistor : Resistive sensor (AC bias) SEN1 S1C17 RFC : Reference capacitor Figure 18.2.2.2 Connection Example in Resistive Sensor AC Oscillation Mode Seiko Epson Corporation 18-2 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 232

    (Clear interrupt flags) - Set the interrupt enable bits in the RFCnINTE register to 1. (Enable interrupts) 3. Assign the RFC input/output function to the ports. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 18-3 TECHNICAL MANUAL (Rev. 1.0)

  • Page 233: Operating Modes

    To obtain the difference between the reference oscillation and sensor oscillation clock count values from the measurement counter simply, appropriate initial values must be set to the measurement counter before starting reference oscillation. Seiko Epson Corporation 18-4 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 234: Converting Operations And Control Procedure

    The measurement counter overflow sets the RFCnINTF.EREFIF bit to 1 indicating that the reference oscil- lation has been terminated normally. If the RFCnINTE.EREFIE bit = 1, a reference oscillation completion interrupt request occurs at this point. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 18-5...

  • Page 235

    Performing reference oscillation and sensor oscillation with the same resistor and capacitor results n ≈ m. The difference between n and m is a conversion error. Table 18.4.4.1 lists the error factors. (n: measurement counter initial value, m: measurement counter value at the end of sensor oscillation) Seiko Epson Corporation 18-6 S1C17M20/M21/M22/M23/M24/M25...

  • Page 236: Cr Oscillation Frequency Monitoring Function

    The RFC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the in- terrupt controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 18-7...

  • Page 237

    This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock. 1 (R/W): Divided-by-two clock output 0 (R/W): Oscillation clock output For more information, refer to “CR Oscillation Frequency Monitoring Function.” Seiko Epson Corporation 18-8 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 238: Rfc Ch.n Oscillation Trigger Register

    This bit controls CR oscillation for sensor A. This bit also indicates the CR oscillation status. 1 (W): Start oscillation 0 (W): Stop oscillation 1 (R): Being oscillated 0 (R): Stopped Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 18-9 TECHNICAL MANUAL (Rev. 1.0)

  • Page 239: Rfc Ch.n Measurement Counter Low And High Registers

    Note: The time base counter must be set from the low-order value (RFCnTCL.TC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFCnTCH.TC[23:16] bits) is written first. Seiko Epson Corporation 18-10 S1C17M20/M21/M22/M23/M24/M25...

  • Page 240: Rfc Ch.n Interrupt Flag Register

    RFCnINTE.OVTCIE bit: Time base counter overflow error interrupt RFCnINTE.OVMCIE bit: Measurement counter overflow error interrupt RFCnINTE.ESENBIE bit: Sensor B oscillation completion interrupt RFCnINTE.ESENAIE bit: Sensor A oscillation completion interrupt RFCnINTE.EREFIE bit: Reference oscillation completion interrupt Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 18-11 TECHNICAL MANUAL (Rev. 1.0)

  • Page 241: Bit A/d Converter (adc12a)

    2. 16-bit timer underflow trigger 3. External trigger • Can convert multiple analog input signals sequentially. • Can generate conversion completion and overwrite error interrupts. Figure 19.1.1 shows the ADC12A configuration. Table 19.1.1 ADC12A Configuration of S1C17M20/M21/M22/M23/M24/M25 S1C17M20/M23 Item S1C17M21/M24 S1C17M22/M25...

  • Page 242: Input Pins And External Connections

    : acquisition time). Figure 19.3.2.1 shows an equivalent circuit of the analog input portion. ADINnm ADIN ADIN Source impedance : Analog input resistance ADIN : Analog input capacitance ADIN Figure 19.3.2.1 Equivalent Circuit of Analog Input Portion Seiko Epson Corporation 19-2 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 243

    A/D conversion is actually started in sync with CLK_T16_k after a trigger is accepted. Writing 0 to the ADC12_nCTL.ADST bit stops A/D conversion after the one currently being executed has com- pleted. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 19-3 TECHNICAL MANUAL (Rev. 1.0)

  • Page 244: Conversion Mode And Analog Input Pin Settings

    3. Read the A/D conversion result of the analog input m (ADC12_nADmD.ADmD[15:0] bits). 4. Repeat Steps 2 and 3 until terminating A/D conversion. 5. Write 0 to the ADC12_nCTL.ADST bit. The ADC12A stops operating after the A/D conversion currently being executed has completed. Seiko Epson Corporation 19-4 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 245

    ADINn4 ADINn4 ADC12_nAD3D.AD3D[15:0] ADINn3 conversion result (first) ADINn3 conversion result (second) ADC12_nAD4D.AD4D[15:0] ADINn4 conversion result (first) ADINn4 conversion result (second) Cleared Cleared ADC12_nINTF.AD3CIF Cleared Cleared ADC12_nINTF.AD4CIF Figure 19.4.4.1 A/D Conversion Operations Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 19-5 TECHNICAL MANUAL (Rev. 1.0)

  • Page 246

    (ADC12_nTRG.CNVMD = 0). If A/D conversion is stopped after the maximum analog input pin number (different in each model) has been completed, these bits indicate ADINn0. Bit 11 Reserved Seiko Epson Corporation 19-6 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 247: Adc12a Ch.n Trigger/analog Input Select Register

    ENDAIN[2:0] bits ≥ ADC12_nTRG.STAAIN[2:0] bits. Bits 10–8 STAAIN[2:0] These bits set the analog input pin to be A/D converted first. See Table 19.6.1 for the relationship between analog input pins and bit setting values. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 19-7 TECHNICAL MANUAL (Rev. 1.0)

  • Page 248: Adc12a Ch.n Configuration Register

    Note: Make sure that the ADC12_nCTL.BSYSTAT bit is set to 0 before altering the ADC12_nCFG register. Bits 15–2 Reserved Bits 1–0 VRANGE[1:0] These bits set the A/D converter operating voltage range. Seiko Epson Corporation 19-8 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 249: Adc12a Ch.n Interrupt Flag Register

    The following shows the correspondence between the bit and interrupt: ADC12_nINTF.ADmOVIF bit: Analog input signal m A/D conversion result overwrite error interrupt ADC12_nINTF.ADmCIF bit: Analog input signal m A/D conversion completion interrupt Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 19-9 TECHNICAL MANUAL (Rev. 1.0)

  • Page 250: Adc12a Ch.n Interrupt Enable Register

    ADC12A Ch.n Result Register m Register name Bit name Initial Reset Remarks ADC12_nADmD 15–0 ADmD[15:0] 0x0000 – Bits 15–0 ADmD[15:0] These bits are the A/D conversion results of the analog input signal m. Seiko Epson Corporation 19-10 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 251

    %rs[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,%rs imm7[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,imm7 Output mode setting value Operation mode setting value Figure 20.2.1 Mode Setting Register Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 20-1 TECHNICAL MANUAL (Rev. 1.0)

  • Page 252

    16 bits Argument 1 32 bits Operation result S1C17 Core Operation result Operation result register 1 register 0 Selector Coprocessor output (16 bits) Flag output Figure 20.3.1 Data Path in Multiplication Mode Seiko Epson Corporation 20-2 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 253

    16 bits Argument 1 32 bits Operation result S1C17 Core Operation result Operation result register 1 register 0 Selector Coprocessor output Flag output Figure 20.4.1 Data Path in Initialize Mode 2 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 20-3 TECHNICAL MANUAL (Rev. 1.0)

  • Page 254

    %rd ← res1[31:16] (Remainder) (ext res0[31:0] ÷ {%rd, imm7/16} imm9) res0[31:0] ← Quotient ld.ca %rd,imm7 res1[31:0] ← Remainder %rd ← res1[31:16] (Remainder) res0: operation result register 0, res1: operation result register 1 Seiko Epson Corporation 20-4 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 255

    COPRO2 Argument 2 16 bits Argument 1 32 bits S1C17 Core Operation result Operation result register 1 register 0 Selector Coprocessor output Flag output Figure 20.5.1 Data Path in Initialize Mode Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 20-5 TECHNICAL MANUAL (Rev. 1.0)

  • Page 256

    %r0. ld.cw %r0,0x13 ; Sets the mode (operation result read mode and 16 high-order bits output mode 0). ; Loads the 16 high-order bits of the result to %r1. ld.ca %r1,%r0 Seiko Epson Corporation 20-6 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 257

    %rd ← res1[15:0] ld.ca %rd,%rs ld.ca %rd,imm7 %rd ← res1[15:0] 0x33 %rd ← res1[31:16] ld.ca %rd,%rs ld.ca %rd,imm7 %rd ← res1[31:16] res0: operation result register 0, res1: operation result register 1 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 20-7 TECHNICAL MANUAL (Rev. 1.0)

  • Page 258

    *2 R is not required when using the DSIO pin as a general-purpose I/O port. *3 Normally, C is not required, as V is supplied externally. VREFA REFA Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 21-1 TECHNICAL MANUAL (Rev. 1.0)

  • Page 259

    *1 OSC1 oscillator: CLGOSC1.OSC1SELCR bit = 0, CLGOSC1.INV1N[1:0] bits = 0x0, CLGOSC1.CGI1[2:0] bits = 0x0, CLGOSC1. OSDEN bit = 0, C = 0 pF, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), = 7 pF) *2 OSC1 oscillator: CLGOSC1.OSC1SELCR bit = 1...

  • Page 260

    IOSC = OFF, OSC1 = 32.768 kHz, OSC3 = ON, Ta = 25°C, Typ. value 2,800 2,400 20 MHz (0x3) 16 MHz (0x2) 2,000 12 MHz (0x1) 1,600 1,200 ( ) Value of the FLASHCWAIT.RDWAIT[1:0] bits Ta [°C] Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 21-3 TECHNICAL MANUAL (Rev. 1.0)

  • Page 261

    = 1.8 to 5.5 V, V = 0 V, Ta = -40 to 85°C Item Symbol Condition Min. Typ. Max. Unit Oscillation start time – – µs Oscillation frequency 25°C IOSC -40 to 85°C Seiko Epson Corporation 21-4 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 262

    Internal oscillator CLGOSC1.OSC1SELCR bit = 1 31.04 32.96 OSC1I oscillation frequency *1 CLGOSC1.CGI1[2:0] bits = 0x0, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 21-5 TECHNICAL MANUAL (Rev. 1.0)

  • Page 263

    *2 Ceramic resonator = CSBLA_J (manufactured by Murata Manufacturing Co., Ltd., 1 MHz), C = 100 pF OSC3 internal oscillation frequency-temperature characteristic Typ. value 20MHz 16 MHz 12 MHz Ta [°C] Seiko Epson Corporation 21-6 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 264

    P00–07, P10–17, P20–27, P30–37, P40–42, PD0–D1, PD3–D4 Pin capacitance P00–07, P10–17, P20–27, P30–37, P40–42, PD0–D1, PD3–D4 – – High level Low level 7.0 V* Input voltage [V] (∗ For over voltage tolerant fail-safe type port) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 21-7 TECHNICAL MANUAL (Rev. 1.0)

  • Page 265

    1.85 SVDCTL.SVDC[4:0] bits = 0x05 1.95 2.05 SVDCTL.SVDC[4:0] bits = 0x06 2.05 2.15 SVDCTL.SVDC[4:0] bits = 0x07 2.15 2.26 SVDCTL.SVDC[4:0] bits = 0x08 2.24 2.36 SVDCTL.SVDC[4:0] bits = 0x09 2.34 2.46 Seiko Epson Corporation 21-8 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 266

    CLK_SVD3 = 32 kHz, Ta = 25°C *1 If CLK_SVD3 is configured in the neighborhood of 32 kHz, the SVDINTF.SVDDT bit is masked during the t period and it re- SVDEN tains the previous value. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 21-9 TECHNICAL MANUAL (Rev. 1.0)

  • Page 267

    – – #SPISSn High pulse width – – SDOn output start time – – = 30 pF SDOn output stop time – – = 30 pF *1 C = Pin load Seiko Epson Corporation 21-10 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 268

    * After this period, the first clock pulse is generated. SU:DAT SDAn HD:DAT SU:STA SU:STO HIGH HD:STA SCLn HD:STA S: START condition Sr: Repeated START condition 1st clock cycle 9th clock cycle P: STOP condition Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 21-11 TECHNICAL MANUAL (Rev. 1.0)

  • Page 269

    = 100 kW, Ta = 25°C, Typ. value 10,000 10,000 1,000 1,000 5.5 V 5.5 V 3.6 V 3.6 V 1.8 V 1.8 V ∆f ∆f /∆IC /∆IC RFCLK RFCLK 1,000 10,000 1,000 10,000 100,000 [kΩ] [pF] Seiko Epson Corporation 21-12 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 270

    *1 The Max. value is the value when the A/D conversion clock frequency f = 2,000 kHz. CLK_ADC12A *2 Integral nonlinearity is measured at the end point line. *3 The error will be increased according to the potential difference between V and VREFAn. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 21-13 TECHNICAL MANUAL (Rev. 1.0)

  • Page 271

    , ADIN = V /2, f = 100 ksps, Ta = 25°C, Typ. value REFA REFA 1,000 ADC12_nCFG.VRANGE[1:0] bits = 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 REFA Seiko Epson Corporation 21-14 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 272

    *2: For Flash programming (when V is generated internally) *3: When the OSC1 crystal oscillator is used (except for the S1C17M20/M23 (24-pin package)) *4: When the OSC3 crystal/ceramic oscillator is used (except for the S1C17M20/M23 (24-pin package)) *5: When the R/F converter is used (available in the S1C17M22/M25) ( ): Do not mount components if unnecessary.

  • Page 273

    Symbol Name Recommended components X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by Seiko Epson Corporation OSC1 gate capacitor Trimmer capacitor or ceramic capacitor OSC1 drain capacitor Ceramic capacitor X’tal3 Crystal resonator...

  • Page 274

    23 PACKAGE 23 Package SQFN4-24 package (S1C17M20/M23) (Unit: mm) Top View /4.1 INDEX Bottom View /2.6 C0.3 EXPOSED DIE PAD 0.35 /0.45 Figure 23.1 SQFN4-24 Package Dimensions * The potential of the EXPOSED DIE PAD is the same as that of the substrate potential (V ) on the back of the IC.

  • Page 275

    23 PACKAGE SQFN5-32 package (S1C17M20/M23) (Unit: mm) Top View /5.1 INDEX Bottom View /3.2 C0.3 EXPOSED DIE PAD 0.35 /0.45 Figure 23.2 SQFN5-32 Package Dimensions * The potential of the EXPOSED DIE PAD is the same as that of the substrate potential (V ) on the back of the IC.

  • Page 276

    23 PACKAGE TQFP12-32pin package (S1C17M21/M24) (Unit: mm) INDEX 0.32 /0.42 0.09 /0.2 0° /10° /0.7 Figure 23.3 TQFP12-32pin Package Dimensions TQFP12-48pin package (S1C17M20/M21) (Unit: mm) INDEX 0.17 /0.27 0.09 /0.2 0° /10° /0.7 Figure 23.1 QFP12-48pin Package Dimensions Seiko Epson Corporation...

  • Page 277

    – 5–4 CLKDIV[1:0] R/WP 3–2 – – 1–0 CLKSRC[1:0] R/WP 0x4042 CLGOSC 15–12 – – – (CLG Oscillation EXOSCSLPC Control Register) OSC3SLPC OSC1SLPC IOSCSLPC 7–4 – – EXOSCEN OSC3EN OSC1EN IOSCEN Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-1 TECHNICAL MANUAL (Rev. 1.0)

  • Page 278

    2–0 ILV0[2:0] Supply voltage detector interrupt (ILVSVD3) 0x4082 ITCLV1 15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV3[2:0] Clock generator interrupt Setup Register 1) (ILVCLG) 7–0 – 0x00 – – Seiko Epson Corporation AP-A-2 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 279

    15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV21[2:0] – 12-bit A/D converter Setup Register 10) interrupt (ILVADC12A_0) 7–3 – 0x00 – – 2–0 ILV20[2:0] – 16-bit timer Ch.3 interrupt (ILVT16_3) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-3 TECHNICAL MANUAL (Rev. 1.0)

  • Page 280

    11–8 RTCHLA[3:0] – – 6–4 RTCMIHA[2:0] 3–0 RTCMILA[3:0] 0x40c6 RTCSWCTL 15–12 BCD10[3:0] – (RTC Stopwatch 11–8 BCD100[3:0] Control Register) 7–5 – – SWRST Read as 0. 3–1 – – – SWRUN Seiko Epson Corporation AP-A-4 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 281

    1DAYIF 1HURIF 1MINIF 1SECIF 1_2SECIF 1_4SECIF 1_8SECIF 1_32SECIF 0x40d2 RTCINTE RTCTRMIE – (RTC Interrupt Enable SW1IE Register) SW10IE SW100IE 11–9 – – ALARMIE 1DAYIE 1HURIE 1MINIE 1SECIE 1_2SECIE 1_4SECIE 1_8SECIE 1_32SECIE Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-5 TECHNICAL MANUAL (Rev. 1.0)

  • Page 282

    (T16 Ch.0 Interrupt 7–1 – 0x00 – Flag Register) UFIF Cleared by writing 1. 0x416c T16_0INTE 15–8 – 0x00 – – (T16 Ch.0 Interrupt 7–1 – 0x00 – Enable Register) UFIE Seiko Epson Corporation AP-A-6 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 283

    ✓ P0REN5 – – – ✓ P0REN4 – – – ✓ P0REN3 ✓ ✓ ✓ ✓ P0REN2 ✓ ✓ ✓ ✓ P0REN1 ✓ ✓ ✓ ✓ P0REN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-7 TECHNICAL MANUAL (Rev. 1.0)

  • Page 284

    ✓ 9–8 P04MUX[1:0] – – – ✓ 7–6 P03MUX[1:0] ✓ ✓ ✓ ✓ 5–4 P02MUX[1:0] ✓ ✓ ✓ ✓ 3–2 P01MUX[1:0] ✓ ✓ ✓ ✓ 1–0 P00MUX[1:0] ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-8 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 285

    ✓ P1IF5 ✓ ✓ ✓ ✓ P1IF4 ✓ ✓ ✓ ✓ P1IF3 ✓ ✓ ✓ ✓ P1IF2 ✓ ✓ ✓ ✓ P1IF1 – ✓ ✓ ✓ P1IF0 – ✓ ✓ ✓ Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-9 TECHNICAL MANUAL (Rev. 1.0)

  • Page 286

    ✓ 9–8 P14MUX[1:0] ✓ ✓ ✓ ✓ 7–6 P13MUX[1:0] ✓ ✓ ✓ ✓ 5–4 P12MUX[1:0] ✓ ✓ ✓ ✓ 3–2 P11MUX[1:0] – ✓ ✓ ✓ 1–0 P10MUX[1:0] – ✓ ✓ ✓ Seiko Epson Corporation AP-A-10 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 287

    ✓ P2IF5 ✓ ✓ ✓ ✓ P2IF4 ✓ ✓ ✓ ✓ P2IF3 – ✓ ✓ ✓ P2IF2 – ✓ ✓ ✓ P2IF1 – – – ✓ P2IF0 – – – ✓ Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-11 TECHNICAL MANUAL (Rev. 1.0)

  • Page 288

    ✓ 9–8 P24MUX[1:0] ✓ ✓ ✓ ✓ 7–6 P23MUX[1:0] – ✓ ✓ ✓ 5–4 P22MUX[1:0] – ✓ ✓ ✓ 3–2 P21MUX[1:0] – – – ✓ 1–0 P20MUX[1:0] – – – ✓ Seiko Epson Corporation AP-A-12 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 289

    ✓ P3IF5 – – – ✓ P3IF4 – – – ✓ P3IF3 – – – ✓ P3IF2 ✓ ✓ ✓ ✓ P3IF1 ✓ ✓ ✓ ✓ P3IF0 ✓ ✓ ✓ ✓ Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-13 TECHNICAL MANUAL (Rev. 1.0)

  • Page 290

    ✓ 9–8 P34MUX[1:0] – – – ✓ 7–6 P33MUX[1:0] – – – ✓ 5–4 P32MUX[1:0] ✓ ✓ ✓ ✓ 3–2 P31MUX[1:0] ✓ ✓ ✓ ✓ 1–0 P30MUX[1:0] ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-14 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 291

    (P4 Port Function 7–6 – – – – – – Select Register) 5–4 P42MUX[1:0] – – – – ✓ 3–2 P41MUX[1:0] – – – ✓ 1–0 P40MUX[1:0] – – – ✓ Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-15 TECHNICAL MANUAL (Rev. 1.0)

  • Page 292

    (P Port Clock Control DBRUN R/WP – ✓ ✓ ✓ ✓ Register) 7–4 CLKDIV[3:0] R/WP ✓ ✓ ✓ ✓ 3–2 KRSTCFG[1:0] R/WP ✓ ✓ ✓ ✓ 1–0 CLKSRC[1:0] R/WP ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-16 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 293

    ✓ ✓ ✓ Port Multiplexer 10–8 P15PERISEL[2:0] ✓ ✓ ✓ ✓ Setting Register) 7–5 P14PPFNC[2:0] ✓ ✓ ✓ ✓ 4–3 P14PERICH[1:0] ✓ ✓ ✓ ✓ 2–0 P14PERISEL[2:0] ✓ ✓ ✓ ✓ Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-17 TECHNICAL MANUAL (Rev. 1.0)

  • Page 294

    – – ✓ Port Multiplexer 10–8 P37PERISEL[2:0] – – – ✓ Setting Register) 7–5 P36PPFNC[2:0] – – – ✓ 4–3 P36PERICH[1:0] – – – ✓ 2–0 P36PERISEL[2:0] – – – ✓ Seiko Epson Corporation AP-A-18 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 295

    – (UART3 Ch.0 Inter- – – rupt Enable Register) TENDIE FEIE PEIE OEIE RB2FIE RB1FIE TBEIE 0x4390 UA0CAWF 15–8 – 0x00 – – (UART3 Ch.0 Carrier 7–0 CRPER[7:0] 0x00 Waveform Register) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-19 TECHNICAL MANUAL (Rev. 1.0)

  • Page 296

    (SPIA Ch.0 Control 7–2 – 0x00 – Register) SFTRST MODEN 0x43b4 SPI0TXD 15–0 TXD[15:0] 0x0000 – (SPIA Ch.0 Transmit Data Register) 0x43b6 SPI0RXD 15–0 RXD[15:0] 0x0000 – (SPIA Ch.0 Receive Data Register) Seiko Epson Corporation AP-A-20 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 297

    MODEN 0x43cc I2C0TXD 15–8 – 0x00 – – (I2C Ch.0 Transmit 7–0 TXD[7:0] 0x00 Data Register) 0x43ce I2C0RXD 15–8 – 0x00 – – (I2C Ch.0 Receive 7–0 RXD[7:0] 0x00 Data Register) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-21 TECHNICAL MANUAL (Rev. 1.0)

  • Page 298

    Counter Data Register) 0x5006 T16B0TC 15–0 TC[15:0] 0x0000 – (T16B Ch.0 Timer Counter Data Register) 0x5008 T16B0CS 15–8 – 0x00 – – (T16B Ch.0 Counter 7–4 – – Status Register) CAPI1 CAPI0 UP_DOWN Seiko Epson Corporation AP-A-22 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 299

    16-bit PWM Timer (T16B) Ch.1 Address Register name Bit name Initial Reset Remarks 0x5040 T16B1CLK 15–9 – 0x00 – – (T16B Ch.1 Clock DBRUN Control Register) 7–4 CLKDIV[3:0] – – 2–0 CLKSRC[2:0] Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-23 TECHNICAL MANUAL (Rev. 1.0)

  • Page 300

    14–12 CBUFMD[2:0] Capture 0 Control 11–10 CAPIS[1:0] Register) 9–8 CAPTRG[1:0] – – TOUTMT TOUTO 4–2 TOUTMD[2:0] TOUTINV CCMD 0x5052 T16B1CCR0 15–0 CC[15:0] 0x0000 – (T16B Ch.1 Compare/ Capture 0 Data Register) Seiko Epson Corporation AP-A-24 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 301

    0x5208 UA1TXD 15–8 – 0x00 – – (UART3 Ch.1 Trans- 7–0 TXD[7:0] 0x00 mit Data Register) 0x520a UA1RXD 15–8 – 0x00 – – (UART3 Ch.1 Receive 7–0 RXD[7:0] 0x00 Data Register) Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 302

    (T16 Ch.2 Interrupt 7–1 – 0x00 – Flag Register) UFIF Cleared by writing 1. 0x526c T16_2INTE 15–8 – 0x00 – – (T16 Ch.2 Interrupt 7–1 – 0x00 – Enable Register) UFIE Seiko Epson Corporation AP-A-26 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 303

    1–0 MOSEL[1:0] 0x5304 SNDCTL 15–9 – 0x00 – – (SNDA Control SSTP Register) 7–1 – 0x00 – MODEN 0x5306 SNDDAT MDTI – (SNDA Data MDRS Register) 13–8 SLEN[5:0] 0x00 7–0 SFRQ[7:0] 0xff Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-27 TECHNICAL MANUAL (Rev. 1.0)

  • Page 304

    CRST bit. 0x532c REMINTE 15–8 – 0x00 – – (REMC3 Interrupt 7–2 – 0x00 – Enable Register) DBIE APIE 0x5330 REMCARR 15–8 CRDTY[7:0] 0x00 – (REMC3 Carrier 7–0 CRPER[7:0] 0x00 Waveform Register) Seiko Epson Corporation AP-A-28 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 305

    Flag Register) OVTCIF Cleared by writing 1. OVMCIF ESENBIF ESENAIF EREFIF 0x5450 RFC0INTE 15–8 – 0x00 – – (RFC Ch.0 Interrupt 7–5 – – Enable Register) OVTCIE OVMCIE ESENBIE ESENAIE EREFIE Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-29 TECHNICAL MANUAL (Rev. 1.0)

  • Page 306

    Flag Register) OVTCIF Cleared by writing 1. OVMCIF ESENBIF ESENAIF EREFIF 0x5470 RFC1INTE 15–8 – 0x00 – – (RFC Ch.1 Interrupt 7–5 – – Enable Register) OVTCIE OVMCIE ESENBIE ESENAIE EREFIE Seiko Epson Corporation AP-A-30 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 307

    ✓ 0x54a6 ADC12_0CFG 15–8 – 0x00 – – – – – – (ADC12A Ch.0 Con- 7–2 – 0x00 – – – – – figuration Register) 1–0 VRANGE[1:0] ✓ ✓ ✓ ✓ Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-31 TECHNICAL MANUAL (Rev. 1.0)

  • Page 308

    Result Register 5) 0x54b8 ADC12_0AD6D 15–0 AD6D[15:0] 0x0000 – – – – ✓ (ADC12A Ch.0 Result Register 6) 0x54ba ADC12_0AD7D 15–0 AD7D[15:0] 0x0000 – – – – ✓ (ADC12A Ch.0 Result Register 7) Seiko Epson Corporation AP-A-32 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 309

    APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS 0xffff90 Debugger (DBG) Address Register name Bit name Initial Reset Remarks 0xffff90 DBRAM 31–24 – 0x00 – – (Debug RAM Base 23–0 DBRAM[23:0] 0x00 Register) 07c0 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-A-33 TECHNICAL MANUAL (Rev. 1.0)

  • Page 310: Appendix B Power Saving

    • Using a crystal resonator with lower C value decreases current consumption. However, these configurations may reduce the oscillation margin and increase the frequency error, therefore, be sure to perform matching evaluation using the actual printed circuit board. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-B-1 TECHNICAL MANUAL (Rev. 1.0)

  • Page 311: B.2 Other Power Saving Methods

    Continuous operation mode (SVDCTL.SVDMD[1:0] bits = 0x0) always detects the power supply voltage, therefore, it increases current consumption. Set the supply voltage detector to intermittent operation mode or turn it on only when required. Seiko Epson Corporation AP-B-2 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 312: Appendix C Mounting Precautions

    V should be placed as close to the V pin as possible and use a sufficiently thick wiring pattern that allows current of several tens of mA to flow. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-C-1 TECHNICAL MANUAL (Rev. 1.0)

  • Page 313

    (2) When not soldering exposed die pad to mounting board Do not place any signal wiring pattern on the exposed die pad area of the mounting board. Seiko Epson Corporation AP-C-2 S1C17M20/M21/M22/M23/M24/M25...

  • Page 314

    (2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-C-3 TECHNICAL MANUAL (Rev. 1.0)

  • Page 315: Appendix D Measures Against Noise

    • Execute the resending process via software after executing the receive error handler with a parity check. For details of the pin functions and the function switch control, see the “I/O Ports” chapter. For the UART con- trol and details of receive errors, see the “UART” chapter. Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-D-1...

  • Page 316: Appendix E Initialization Routine

    %r1, 0x41b0 ; FLASHC register address ; Flash read wait cycle Xld.a %r0, 0x00 ; 0x00 = No wait ...(5) ld.b [%r1], %r0 ; [0x41b0] <= 0x00 ; ===== Main routine ========================================= Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25 AP-E-1 TECHNICAL MANUAL (Rev. 1.0)

  • Page 317

    “intXX_handler” can be used for software interrupts. (3) The program code is written in the “.text” section. (4) Sets the stack pointer. (5) Sets the number of Flash memory read cycles. (See the “Memory and Bus” chapter.) Seiko Epson Corporation AP-E-2 S1C17M20/M21/M22/M23/M24/M25 TECHNICAL MANUAL (Rev. 1.0)

  • Page 318

    REVISION HISTORY Revision History Code No. Page Contents 413557000 New establishment...

  • Page 319

    Phone: +49-89-14005-0 Fax: +49-89-14005-110 Keyuan South RD (Shenzhen bay), Nanshan District, Shenzhen 518054, CHINA Phone: +86-10-3299-0588 Fax: +86-10-3299-0560 EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110, TAIWAN Phone: +886-2-8786-6688 Fax: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD.

This manual also for:

S1c17m25, S1c17m21, S1c17m22, S1c17m23, S1c17m24

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