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20.6. Control Registers
RFC Ch.n Clock Control Register
Register name
Bit
RFC_nCLK
15–9
8
7–6
5–4
3–2
1–0
Bits 15–9
Reserved
Bit 8
DBRUN
This bit sets whether the RFC operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bits 7–6
Reserved
Bits 5–4
CLKDIV[1:0]
These bits select the division ratio of the RFC operating clock.
Bits 3–2
Reserved
Bits 1–0
CLKSRC[1:0]
These bits select the clock source of the RFC.
RFC_nCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note:
The RFC_nCLK register settings can be altered only when the RFC_nCTL.MODEN bit = 0.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
–
0x00
DBRUN
1
–
0x0
CLKDIV[1:0]
0x0
–
0x0
CLKSRC[1:0]
0x0
Table 20.6.1 Clock Source and Division Ratio Settings
RFC_nCLK.CLKSRC[1:0] bits
0x0
IOSC
1/8
1/4
1/2
1/1
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/W
–
R
H0
R/W
–
R
H0
R/W
0x1
0x2
OSC1
OSC3
1/1
1/8
1/4
1/2
1/1
Remarks
–
0x3
EXOSC
1/1
20-9
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