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Data reception using DMA
By setting the UART3_nRB1FDMAEN.RB1FDMAENx bit to 1 (DMA transfer request enabled), a
DMA transfer request is sent to the DMA controller and the received data is transferred from the
UART3_nRXD register to the specified memory via DMA Ch.x when the UART3_nINTF.RB1FIF bit is
set to 1 (receive buffer one byte full).
This automates the procedure (read by one byte) described above.
The transfer source/destination and control data must be set for the DMA controller and the
relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on
DMA, refer to the "DMA Controller" chapter.
Table 13.5.3.1 DMA Data Structure Configuration Example (for Data Reception)
Item
End pointer
Transfer source
Transfer destination
Control data
dst_inc
dst_size
src_inc
src_size
R_power
n_minus_1
cycle_ctrl
13.5.4. IrDA Interface
This UART3 includes an RZI modulator/demodulator circuit enabling implementation of IrDA 1.0-
compatible infrared communication function simply by adding simple external circuits.
Set the UART3_nMOD.IRMD bit to 1 to use the IrDA interface.
Data transfer control is identical to that for normal interface even if the IrDA interface function is enabled.
Figure 13.5.4.1 Example of Connections with an Infrared Communication Module
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
UART3_nRXD register address
Memory address to which the last received data is stored
0x0 (+1)
0x0 (byte)
0x3 (no increment)
0x0 (byte)
0x0 (arbitrated for every transfer)
Number of transfer data
0x1 (basic transfer)
RXD
USINn
VCC
V
DD
GND
V
SS
TXD
USOUTn
LEDA
S1C31 UART3
Infrared communication module
Seiko Epson Corporation
Setting example
VCC
AMP
GND
13-9
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