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17.4.2. Counter Block Operations
The counter in each counter block channel is a 16-bit up/down counter that counts the selected
operating clock (count clock).
Count mode
The T16B_nCTL.CNTMD[1:0] bits allow selection of up, down, and up/down mode. The
T16B_nCTL.ON- EST bit allows selection of repeat and one-shot mode. The counter operates in six
counter modes specified with a combination of these modes.
Repeat mode enables the counter to continue counting until stopped via software. Select this mode
to generate periodic interrupts at desired intervals or to generate timer output waveforms.
One-shot mode enables the counter to stop automatically. Select this mode to stop the counter after
an interrupt has occurred once, such as for measuring pulse width or external event intervals and
checking a specific lapse of time.
Up, down, and up/down mode configures the counter as an up counter, down counter and up/down
counter, respectively.
MAX counter data register
The MAX counter data register (T16B_nMC.MC[15:0] bits) is used to set the maximum value of the
counter (hereafter referred to as MAX value). This setting limits the count range to 0x0000–MAX value
and determines the count and interrupt cycles. When the counter is set to repeat mode, the MAX
value can be rewritten in the procedure shown below even if the counter is running.
1. Check to see if the T16B_nCTL.MAXBSY bit is set to 0.
2. Write the MAX value to the T16B_nMC.MC[15:0] bits.
Note:
When rewriting the MAX value, the new MAX value should be written after the counter has been
reset to the previously set MAX value.
Counter reset
Setting the T16B_nCTL.PRESET bit to 1 resets the counter. This clears the counter to 0x0000 in up or
up/down mode, or presets the MAX value to the counter in down mode.
The counter is also cleared to 0x0000 when the counter value exceeds the MAX value during
count up operation.
Counting start
To start counting, set the T16B_nCTL.RUN bit to 1. The counting stop control depends on the count
mode set.
Counter value read
The counter value can be read out from the T16B_nTC.TC[15:0] bits. However, since T16B operates on
CLK_ T16Bn, one of the operations shown below is required to read correctly by the CPU.
Read the counter value twice or more and check to see if the same value is read.
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Stop the timer and then read the counter value.
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Counter status check
The counter operating status can be checked using the T16B_nCS.BSY bit. The T16B_nCS.BSY bit is
set to 1 while the counter is running or 0 while the counter is idle.
The current count direction can also be checked using the T16B_nCS.UP_DOWN bit. The
T16B_nCS.UP_ DOWN bit is set to 1 during count up operation or 0 during count down operation.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Seiko Epson Corporation
17-5
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