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Table 15.5.5.1 DMA Data Structure Configuration Example (for Writing 16-bit Dummy Transmit Data)
Item
End pointer
Control data
Table 15.5.5.2 DMA Data Structure Configuration Example (for 16-bit Data Reception)
Item
End pointer
Control data
The following shows an example of the control procedure including the DMA controller operations:
1. Configure the primary data structure for the DMA channel (Ch.x) used for writing dummy
bytes to the QSPI_nTXD register as shown in Table 15.5.5.1.
2. Configure the primary data structure for the DMA channel (Ch.y) used for reading data from
the QSPI_nRXD register as shown in Table 15.5.5.2.
3. Enable both the DMA channels using the DMA controller register.
4. Increase the priority of the DMA channel used for reading data using the DMA controller register.
5. Clear the channel request masks for both the DMA channels using the DMA controller register.
6. Clear the DMA transfer completion interrupt flags using the DMA controller register.
7. Enable only the DMA transfer completion interrupt of the DMA channel used for reading using
the DMA controller register.
8. Clear pending DMA interrupts in the CPU core.
9. Enable pending DMA interrupts in the CPU core.
10. Enable the QSPI to issue DMA transfer requests to both the DMA channels using the
QSPI_nTBEDMAEN.TBEDMAENx and QSPI_nRBFDMAEN.RBFDMAENy bits.
11. Assert the slave select signal by controlling the QSPI_nCTL.MSTSSO bit, or the general-purpose
output port used for an extra slave select signal output (if necessary).
12. Issue a software DMA transfer request to the DMA channel used for writing dummy bytes by
setting the DMA controller register. This operation is required to read the first data and to set
the receive buffer full status flag. Once the receive buffer full status flag is set, a hardware
DMA request is generated, and the DMA controller transfers data from the QSPI_nRXD register
and then writes another dummy byte to the QSPI_nTXD register, allowing the QSPI to read the
next data.
13. Wait for a DMA interrupt.
14. Disable the DMA requests to be sent to both the DMA channels using the
QSPI_nTBEDMAEN.TBEDMAENx and QSPI_nRBFDMAEN.RBFDMAENy bits.
15. Set the channel request masks for both the DMA channels using the DMA controller register.
16. Disable both the DMA channels using the DMA controller register.
17. Negate the slave select signal by controlling the QSPI_nCTL.MSTSSO bit or the general-purpose
output port (if necessary).
15.5.6. Data Reception in Memory Mapped Access Mode
15-18
Transfer source
Memory address in which dummy data is stored
Transfer destination
QSPI_nTXD register address
dst_inc
0x3 (no increment)
dst_size
0x1 (haflword)
src_inc
0x3 (no increment)
src_size
0x1 (halfword)
R_power
0x0 (arbitrated for every transfer)
n_minus_1
Number of transfer data
cycle_ctrl
0x1 (basic transfer)
Transfer source
QSPI_nRXD register address
Transfer destination
Memory address to which the last received data is stored
dst_inc
0x1 (+2)
dst_size
0x1 (haflword)
src_inc
0x3 (no increment)
src_size
0x1 (halfword)
R_power
0x0 (arbitrated for every transfer)
n_minus_1
Number of transfer data
cycle_ctrl
0x1 (basic transfer)
Seiko Epson Corporation
Setting example
Setting example
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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