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12.4.4. Operations in One-shot Mode
T16 Ch.n enters one-shot mode by setting the T16_nMOD.TRMD bit to 1.
In one-shot mode, the count operation starts by writing 1 to the T16_nCTL.PRUN bit and stops after the
T16_nTR register value is preset to the counter when an underflow has occurred. At the same time the
counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter
after an interrupt has occurred once, such as for checking a specific lapse of time.
0xffff
Counter
0x0000
Software control
Underflow interrupt
12.4.5. Counter Value Read
The counter value can be read out from the T16_nTC.TC[15:0] bits. However, since T16 operates on
CLK_T16_n, one of the operations shown below is required to read correctly by the CPU.
Read the counter value twice or more and check to see if the same value is read.
-
Stop the timer and then read the counter value.
-
12.5. Interrupt
Each T16 channel has a function to generate the interrupt shown in Table 12.5.1.
Interrupt
Underflow
T16 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to
the CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable
bit, is set. For more information on interrupt control, refer to the "Interrupt" chapter.
12-4
Underflow cycle
PRESET = 1
PRUN = 1
PRUN = 1
Figure 12.4.4.1 Count Operations in One-shot Mode
Table 12.5.1 T16 Interrupt Function
Interrupt flag
T16_nINTF.UFIF
Seiko Epson Corporation
PRUN = 1
PRUN = 1
PRUN = 0
Set condition
When the counter underflows
T16_nTR
register setting
Time
Clear condition
Writing 1
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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