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11.5. SVD3 Interrupt and Reset
11.5.1. SVD3 Interrupt
Setting the SVD3CTL.SVDRE[3:0] bits to a value other than 0xa allows use of the low power supply
voltage detection interrupt function.
Table 11.5.1.1 Low Power Supply Voltage Detection Interrupt Function
Interrupt
SVD3INTF.SVDIF
Low power supply
voltage detection
SVD3 provides the interrupt enable bit (SVD3INTE.SVDIE bit) corresponding to the interrupt flag
(SVD3INTF. SVDIF bit). An interrupt request is sent to the COU core only when the SVD3INTF.SVDIF bit is
set while the interrupt is enabled by the SVD3INTE.SVDIE bit. For more information on interrupt control,
refer to the "Interrupt" chapter.
Once the SVD3INTF.SVDIF bit is set, it will not be cleared even if the power supply voltage subsequently
returns to a value exceeding the SVD detection voltage V
interrupt may occur due to a temporary power supply voltage drop, check the power supply voltage
status by reading the SVD3INTF. SVDDT bit in the interrupt handler routine.
11.5.2. SVD3 Reset
Setting the SVD3CTL.SVDRE[3:0] bits to 0xa allows use of the SVD3 reset issuance function.
The reset issuing timing is the same as that of the SVD3INTF.SVDIF bit being set when a low voltage is
detected. After a reset has been issued, SVD3 enters continuous operation mode even if it was
operating in intermittent operation mode, and continues operating. Issuing an SVD3 reset initializes the
port assignment. However, when EXSVDn is being detected, the input of the port for the EXSVDn pin is
sent to SVD3 so that SVD3 will continue the EXSVDn detection operation.
If the power supply voltage reverts to the normal level, the SVD3INTF.SVDDT bit goes 0 and the reset
state is canceled. After that, SVD3 resumes operating in the operation mode set previously via the
initialization routine. During reset state, the SVD3 control bits are set as shown in Table 11.5.2.1.
Control
register
SVD3CLK
SVD3CTL
SVD3INTF
SVD3INTE
11-6
Interrupt flag
In continuous operation mode
When the SVD3INTF.SVDDT bit is 1
In intermittent operation mode
When low power supply voltage is successively detected
the specified number of times
Table 11.5.2.1 SVD3 Control Bits During Reset State
Control bit
DBRUN
Reset to the initial values.
CLKDIV[2:0]
CLKSRC[1:0]
VDSEL
The set value is retained.
SVDSC[1:0]
Cleared to 0. (The set value becomes invalid as SVD3 enters
continuous operation mode.)
SVDC[4:0]
The set value is retained.
SVDRE[3:0]
The set value (0xa) is retained.
EXSEL
The set value is retained.
SVDMD[1:0]
Cleared to 0 to set continuous operation mode.
MODEN
The set value (1) is retained.
SVDIF
The status (1) before being reset is retained.
SVDIE
Cleared to 0.
Seiko Epson Corporation
Set condition
/EXSVD detection voltage V
SVD
Setting
S1C31D50 TECHNICAL MANUAL
Clear condition
Writing 1
. An
SVD_EXT
(Rev. 1.00)
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