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QSPI Ch.n Memory Mapped Access Configuration Register 2
Register name
Bit
QSPI_nMMACFG2 15–12
11–8
7–6
5–4
3–2
1
0
Bits 15–12
DUMDL[3:0]
These bits set the number of clocks for driving the serial data lines during the dummy
cycle output when accessing the external Flash memory in the memory mapped access
mode. This setting is required to output the XIP confirmation bit to Micron Flash
memories or to output the mode byte to Spansion Flash memories.
Table 15.8.5 Settings of Data Line Drive Length during Dummy Cycle
QSPI_nMMACFG2.DUMDL[3:0] bits
These bits must be set to a value smaller than or equal to the
QSPI_nMMACFG2.DUMLN[3:0] bit setting.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
DUMDL[3:0]
0x7
DUMLN[3:0]
0x7
DATTMOD[1:0]
0x0
DUMTMOD[1:0]
0x0
ADRTMOD[1:0]
0x0
ADRCYC
0
MMAEN
0
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko Epson Corporation
Reset
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
Data line drive length
16 clocks
15 clocks
14 clocks
13 clocks
12 clocks
11 clocks
10 clocks
9 clocks
8 clocks
7 clocks
6 clocks
5 clocks
4 clocks
3 clocks
2 clocks
1 clock
Remarks
–
15-41
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